Pith. sign in

REVIEW 1 major objections 5 minor 69 references

DEX: Data Channel Extension for Efficient CNN Inference on Tiny AI Accelerators

T0 review · 1 major / 5 minor · reviewed 2026-08-11 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read Repacking a low-resolution input across 64 channels lifts TinyML image-classification accuracy by 3.5 points while adding no inference latency.

desk verdict A clean, well-measured TinyML trick for using idle processors as extra input channels, but the accuracy gain is partly against a weak nearest-neighbor downsampling baseline. read the letter →

arxiv 2412.06566 v1 pith:2X4ZJJ6N submitted 2024-12-09 cs.LG

Taesik Gong , Fahim Kawsar , Chulhong Min This is my paper · ORCID
classification cs.LG
keywords TinyMLCNNinferenceAIacceleratorsinputchannelextensionimagedownsamplingMAX78000classificationquantization-awaretraining
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Small AI accelerators for TinyML must downsample camera images to fit their limited per-processor memory, discarding most of the picture. This paper proposes DEX, a preprocessing transform that, instead of throwing those pixels away, evenly samples them and stacks the samples into up to 64 input channels for the first convolutional layer. On the MAX78000 and MAX78002 accelerators, where each channel runs on a dedicated processor and memory instance, the extra channels execute in parallel, so on-accelerator inference latency stays the same while the model receives 21.3 times more of the original image. Across four models and four datasets, the paper reports an average accuracy gain of 3.5 percentage points over plain downsampling and 3.6 points over CoordConv, with model size growing by only about 3 percent.

What carries the argument

The load-bearing mechanism is a fixed input transform with two steps. Patch-wise even sampling divides the source image into one patch per output pixel and picks $K = \lceil C_O / C_I \rceil$ sample positions spread evenly inside each patch via $l_k = k \cdot (H_P W_P - 1)/(K - 1)$, so spatial relationships survive both across patches and within a patch. Channel-wise stacking then writes the $k$-th sample of each pixel into consecutive channel slots, producing an input of shape $C_O \times H_O \times W_O$ (for example, 64 × 32 × 32) in which every channel is a spatially consistent view of the whole image. The cost model is what makes the transform free: on the MAX78000 and MAX78002, each of the 64 convolutional processors has a dedicated memory instance, so first-layer processing time depends on the per-channel memory footprint rather than on the total number of channels, up to the 64-channel limit. The only trainable cost is the first layer's weight tensor, which adds roughly 3 percent to the total parameter count.

What would settle it

Run the same 64-channel input through the first CNN layer on an accelerator whose input memory is shared across channels rather than split per processor, and compare latency against the 3-channel baseline; if latency grows with channel count, the no-added-latency part of the claim fails outside the per-processor-memory design. On the paper's own platforms, a timing run in which the 64-channel model at 32 × 32 resolution is slower than the 3-channel model, or an accuracy sweep in which DEX fails to beat downsampling on the same four datasets, would contradict the reported result.

Watch

Extended reading notes

Core claim

On accelerators such as the MAX78000 and MAX78002, the first convolutional layer of a vision CNN is severely underused: a 3-channel RGB input activates only 3 of the 64 parallel processors, while the memory attached to each channel is too small to hold full-resolution images, forcing aggressive downsampling. The paper's central claim is that both problems can be solved at once by changing only the input representation. DEX divides the image into one patch per output pixel, selects within each patch $K = \lceil C_O / C_I \rceil$ pixels at evenly spaced positions given by $l_k = k \cdot (H_P W_P - 1)/(K - 1)$, and stacks those samples across the channel axis, turning a 3 × 32 × 32 input into a 64 × 32 × 32 input. Because the accelerator assigns each input channel its own processor and memory instance, the wider input consumes hardware that was previously idle rather than extra time: measured latency is effectively unchanged (2591 vs 2592 microseconds for SimpleNet), while the fraction of the original image that reaches the network rises from about 1.6 percent to 33 percent. The paper attributes the average accuracy gain of 3.5 percentage points over downsampling and 3.6 points over CoordConv across SimpleNet, WideNet, EfficientNetV2, and MobileNetV2 on ImageNette, Caltech101, Caltech256, and Food101 to this added information, and its ablations show that repeating, rotating, tiling, or sequentially or randomly sampling patches all perform worse than even sampling.

Load-bearing premise

The 'latency stays the same' result rests on the hardware premise that the MAX78000 and MAX78002 process each input channel independently on a dedicated processor with its own memory instance, so first-layer time scales with each channel's size rather than with the total channel count; that is a device-specific behavior validated on these two chips, not a general property of neural-network inference.

Editorial extensions

If this is right

  • Raising the input to the full 64 channels uses processors that otherwise sit idle, so accuracy improves with no on-accelerator latency cost and only about a 3 percent model-size increase.
  • Accuracy generally rises with channel count from 3 to 64, making the largest supported channel size a sensible default on these chips, even though per-dataset optima occasionally sit below 64.
  • DEX feeds up to 21.3 times more of the original image to the network than downsampling does, and can in principle recover all of it when $C_O = C_I \cdot H_I \cdot W_I / (H_O \cdot W_O)$.
  • Deployment adds a preprocessing pass (measured at about 2.2 ms on the board's microcontroller), but because the MCU and the accelerator run in parallel, that cost is hidden whenever inference takes longer than preprocessing.
  • Only the first layer's weights change, so DEX slots into existing quantized training and synthesis pipelines without redesigning the network.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The mechanism depends only on per-channel-parallel first-layer hardware, so the same transform should give accuracy without latency on any accelerator with dedicated per-channel memory slices; running DEX on other per-channel-parallel accelerator chips would test this transfer directly.
  • The paper fixes the channel count at 64 and notes that accuracy occasionally peaks below it, so choosing the channel budget per dataset or model, or adapting it during training, is a natural follow-up that Figure 7 already hints at.
  • Because DEX broadens what each early-layer kernel sees, it acts rather like an input augmentation; combining it with learned downsamplers, or applying it to detection or segmentation heads on the same hardware, are untested extensions.
  • The paper's own power measurements in the appendix show consumption rising with channel count, so on battery-limited devices the real tradeoff is accuracy and energy against unchanged latency, not a fully free improvement.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

1 major / 5 minor

Summary. The paper introduces DEX (Data Channel EXtension), an input transformation for tiny AI accelerators (MAX78000/MAX78002) that, instead of downsampling a high-resolution image to a low-resolution RGB input, evenly samples pixels from each patch of the original image and stacks these samples across up to 64 input channels. The method is fixed (no learned parameters beyond the increased first-layer kernels), and the authors claim that it improves average classification accuracy by 3.5 percentage points over downsampling and 3.6 points over CoordConv across four models and four datasets, while keeping on-accelerator inference latency unchanged. The paper includes ablations comparing repetition, rotation, tiling, and sequential/random patch sampling, and reports standard deviations over three seeds for all main results.

Significance. If the result holds, DEX is a simple, practical, and valuable technique: it exploits the idle per-processor memory instances on tiny AI accelerators to pack more spatial information into the input, with negligible parameter overhead and no accelerator latency penalty. The paper is exemplary in its reproducibility efforts: it provides standard deviations over three seeds, detailed training hyperparameters in Appendix A, a public code repository, and on-device latency measurements on two commercial platforms. The ablations (Table 4) effectively rule out the trivial explanation that merely adding parameters drives the gain, by showing that repetition and rotation do not help while even sampling does. The main caveat is the fairness of the downsampling baseline, which affects the magnitude of the headline accuracy claim.

major comments (1)
  1. [Appendix A.4, Algorithm 1, Eq. (2), Table 1] The 'Downsampling' baseline is implemented as DEX with CO=3, which gives K=1. In Algorithm 1, lk is set to 0 for K=1, so each output pixel is Pij[0,0] — the top-left pixel of each patch. This is nearest-neighbor-style block decimation, not the bilinear, bicubic, or area downsampling that is standard in vision pipelines and that readers will reasonably assume from the term 'downsampling' in the abstract and Table 1. Because the CoordConv baselines also use this same base 3x32x32 image, both of the headline improvements (3.5pp over downsampling and 3.6pp over CoordConv) may be inflated relative to what would be obtained with a standard interpolation-based downsampled input. I recommend adding a proper area-average or bilinear downsampling baseline (and CoordConv on that baseline) to Table 1, or, if that is not feasible, explicitly qualifying the abstract and Section 4.2 as comparing against 'nearest-neighbor-style downsampling' and discussing the likely effect of a stronger baseline on the reported magnitude.
minor comments (5)
  1. [Section 1] The Introduction says 'pair-wise even sampling' where the method is actually 'patch-wise even sampling'; please correct the terminology for consistency with Section 3.2.
  2. [Section 3.1] In the sentence 'an input image with a shape 3 × 224 × 224 (channel, height, and weight)', 'weight' should be 'width'.
  3. [Figure 7] The legend in Figure 7 reads 'SimpletNet' but the model name is 'SimpleNet' throughout the rest of the paper; please fix this typo.
  4. [Appendix C] Figures 11, 12, and 13 appear to be identical (same captions and presumably same images). This seems to be a duplication error; I suggest keeping one figure and removing the duplicates.
  5. [Appendix B.2 / Table 6] Power consumption rises from 53.82 mW to 68.9 mW for SimpleNet as channels increase from 3 to 64 (and similarly for WideNet), but the main text does not mention this side effect. The paper claims 'no increase' only for latency, so this is not contradictory, but a brief mention in Section 4.2 would make the resource-usage discussion more complete.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: DEX is a deterministic input transform with no fitted parameters, and all headline claims are measured against external baselines.

full rationale

The paper's derivation chain is self-contained and empirical. DEX is defined by explicit formulas (Eq. 1-2 and Algorithm 1); the output channel count CO=64 is set by the number of hardware memory instances (Section 3.3), and K is computed from CO and CI. There are no fitted parameters that are later renamed as predictions. Accuracy gains in Table 1 are measured against downsampling, CoordConv, and CoordConv(r), which are external baselines, and Table 4 ablates alternative channel-extension strategies, directly testing whether extra parameters alone explain the gain. The only potentially debatable choice is Appendix A.4's definition of the downsampling baseline as 'equivalent to the case when the number of channels is equal to three in DEX,' combined with Eq. (2)'s lk=0 when K=1, which makes that baseline a nearest-neighbor-style block sample rather than interpolation-based downsampling. That is a benchmarking-fairness concern, not circularity: the reported 3.5pp improvement is an experimental observation, not a quantity forced by definition. The latency claim rests on the empirically validated hardware behavior of MAX78000/78002 (Table 2), not on a circular argument. No load-bearing self-citation or imported uniqueness theorem is present; the self-citations in the related-work and platform-usage sections are contextual only. Overall, no step in the claimed derivation reduces to its own input.

Assumptions & free parameters 1 free parameters · 3 assumptions · 0 invented entities

The central claim is empirical and depends only on hardware architecture assumptions and the choice CO=64. No new physical entities, forces, or fitted constants are introduced. The method's main free choice, the output channel count, is hardware-determined, and the paper includes an ablation over channel counts.

free parameters (1)
  • Output channel count CO for the first layer = 64
    Set to the number of per-processor memory instances (64) on MAX78000/78002, the hardware maximum; not fitted to accuracy data. The paper also scans CO in {6,18,36,64} and finds that higher CO generally helps, so the central 3.5%p result uses CO=64.
assumptions (3)
  • domain assumption MAX78000/78002 have 64 parallel convolutional processors, each with a dedicated memory instance, and per-channel memory is the binding constraint for input resolution.
    Taken from the hardware documentation and prior characterizations cited in Section 2 (e.g., MAX78000 datasheet); the paper's motivation depends on this architecture.
  • domain assumption First-layer inference latency on these accelerators is independent of input channel count up to 64.
    The key premise for the 'no latency increase' claim; empirically confirmed in Table 2 for the two evaluated accelerators, but not proven for other accelerators.
  • domain assumption The official Analog Devices QAT training framework and hyperparameters produce comparable optimization for all compared input formats.
    The comparison assumes the training procedure is not biased toward DEX; hyperparameters are fixed from the official config, and the same procedure is used for baselines.

how reviews work

0 comments
Cite this review

Pith. "Pith review of DEX: Data Channel Extension for Efficient CNN Inference on Tiny AI Accelerators." pith.science (2026). https://pith.science/paper/2X4ZJJ6N

@misc{pith2026241206566,
  author       = {Pith},
  title        = {Pith review of: DEX: Data Channel Extension for Efficient CNN Inference on Tiny AI Accelerators},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/2X4ZJJ6N}},
  note         = {Machine review of arXiv:2412.06566}
}
read the original abstract

Tiny machine learning (TinyML) aims to run ML models on small devices and is increasingly favored for its enhanced privacy, reduced latency, and low cost. Recently, the advent of tiny AI accelerators has revolutionized the TinyML field by significantly enhancing hardware processing power. These accelerators, equipped with multiple parallel processors and dedicated per-processor memory instances, offer substantial performance improvements over traditional microcontroller units (MCUs). However, their limited data memory often necessitates downsampling input images, resulting in accuracy degradation. To address this challenge, we propose Data channel EXtension (DEX), a novel approach for efficient CNN execution on tiny AI accelerators. DEX incorporates additional spatial information from original images into input images through patch-wise even sampling and channel-wise stacking, effectively extending data across input channels. By leveraging underutilized processors and data memory for channel extension, DEX facilitates parallel execution without increasing inference latency. Our evaluation with four models and four datasets on tiny AI accelerators demonstrates that this simple idea improves accuracy on average by 3.5%p while keeping the inference latency the same on the AI accelerator. The source code is available at https://github.com/Nokia-Bell-Labs/data-channel-extension.

Figures

Figures reproduced from arXiv: 2412.06566 by the authors.

Figure 1
Figure 1. The architecture of a tiny AI accelerator (MAX78000 [34]). MAX78000MAX32650 STM32F7 0 500 1000 1500 2000 Latency (ms) 2 13 350 1760 123 754 KWS FaceID MAX78000MAX32650 STM32F7 0 200 400 Energy (mJ) 0.14 0.4 83.7 42.1 47.5 464 KWS FaceID [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 3
Figure 3. Processor utilization with vary￾ing input channels on the AI accelerator. Architecture of tiny AI accelerators. The distinctive characteristic of tiny AI accelerators compared to conven￾tional microcontroller units (MCUs) is parallel processors that parallelize per-channel CNN operations across these processors [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Comparison among different input data. (a) an original image that exceeds the data memory [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figures from the paper (9 more)
Figure 5
Figure 5. Figure 5: Overview of DEX. DEX divides the original image [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]
Figure 6
Figure 6. Figure 6: The initial CNN layer’s operation with DEX. [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]
Figure 7
Figure 7. Figure 7: Accuracy of DEX varying the channel size. The shaded areas are standard deviations. [PITH_FULL_IMAGE:figures/full_fig_p008_7.png]
Figure 8
Figure 8. Figure 8: Resource usage varying the channel size. [PITH_FULL_IMAGE:figures/full_fig_p009_8.png]
Figure 9
Figure 9. Figure 9: Two tiny AI accelerator development platforms used in our work. Note that although [PITH_FULL_IMAGE:figures/full_fig_p015_9.png]
Figure 10
Figure 10. Figure 10: Visulaization of four alternative data extension methods. [PITH_FULL_IMAGE:figures/full_fig_p017_10.png]
Figure 11
Figure 11. Figure 11: Examples images generated from an original [PITH_FULL_IMAGE:figures/full_fig_p019_11.png]
Figure 12
Figure 12. Figure 12: Examples images generated from an original [PITH_FULL_IMAGE:figures/full_fig_p019_12.png]
Figure 13
Figure 13. Figure 13: Examples images generated from an original [PITH_FULL_IMAGE:figures/full_fig_p020_13.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

69 extracted references · 50 canonical work pages

  1. [1]

    Protean: An energy-efficient and heterogeneous platform for adaptive and hardware-accelerated battery-free computing

    Abu Bakar, Rishabh Goel, Jasper de Winkel, Jason Huang, Saad Ahmed, Bashima Islam, Przemysław Pawełczak, Kasım Sinan Yıldırım, and Josiah Hester. Protean: An energy-efficient and heterogeneous platform for adaptive and hardware-accelerated battery-free computing. In Proceedings of the 20th ACM Conference on Embedded Networked Sensor Systems , pages 207–221, 2022

    work page 2022

  2. [2]

    Food-101 – mining discriminative components with random forests

    Lukas Bossard, Matthieu Guillaumin, and Luc Van Gool. Food-101 – mining discriminative components with random forests. In European Conference on Computer Vision, 2014

    2014

  3. [3]

    Large-scale machine learning with stochastic gradient descent

    Léon Bottou. Large-scale machine learning with stochastic gradient descent. In Proceedings of COMPSTAT’2010: 19th International Conference on Computational StatisticsParis France, August 22-27, 2010 Keynote, Invited and Contributed Papers, pages 177–186. Springer, 2010

    work page 2010

  4. [4]

    Once-for-all: Train one network and specialize it for efficient deployment

    Han Cai, Chuang Gan, Tianzhe Wang, Zhekai Zhang, and Song Han. Once-for-all: Train one network and specialize it for efficient deployment. In International Conference on Learning Representations, 2020

    work page 2020

  5. [5]

    Proxylessnas: Direct neural architecture search on target task and hardware

    Han Cai, Ligeng Zhu, and Song Han. Proxylessnas: Direct neural architecture search on target task and hardware. In International Conference on Learning Representations, 2019

    work page 2019

  6. [6]

    Fine-grained hardware acceleration for efficient batteryless intermittent inference on the edge

    Luca Caronti, Khakim Akhunov, Matteo Nardello, Kasım Sinan Yıldırım, and Davide Brunelli. Fine-grained hardware acceleration for efficient batteryless intermittent inference on the edge. ACM Transactions on Embedded Computing Systems, 22(5):1–19, 2023

    work page 2023

  7. [7]

    Pact: Parameterized clipping activation for quantized neural networks

    Jungwook Choi, Zhuo Wang, Swagath Venkataramani, Pierce I-Jen Chuang, Vijayalakshmi Srinivasan, and Kailash Gopalakrishnan. Pact: Parameterized clipping activation for quantized neural networks. arXiv preprint arXiv:1805.06085, 2018

    arXiv 2018

  8. [8]

    https://coral.ai/products/dev-board-micro/

    Google Coral Micro. https://coral.ai/products/dev-board-micro/ . Accessed: 20 May. 2024

    work page 2024

Show all 69 references
  1. [9]

    Imagenet: A large- scale hierarchical image database

    Jia Deng, Wei Dong, Richard Socher, Li-Jia Li, Kai Li, and Li Fei-Fei. Imagenet: A large- scale hierarchical image database. In 2009 IEEE Conference on Computer Vision and Pattern Recognition, pages 248–255, 2009

    2009

  2. [10]

    Sparse: Sparse architecture search for cnns on resource-constrained microcontrollers

    Igor Fedorov, Ryan P Adams, Matthew Mattina, and Paul Whatmough. Sparse: Sparse architecture search for cnns on resource-constrained microcontrollers. Advances in Neural Information Processing Systems, 32, 2019

    2019

  3. [11]

    Learning generative visual models from few training examples: An incremental bayesian approach tested on 101 object categories

    Li Fei-Fei, Rob Fergus, and Pietro Perona. Learning generative visual models from few training examples: An incremental bayesian approach tested on 101 object categories. Computer Vision and Pattern Recognition Workshop, 2004

    2004

  4. [12]

    https://greenwaves-technologies.com/ low-power-processor/

    Greenwaves Technology. https://greenwaves-technologies.com/ low-power-processor/. Accessed: 20 May. 2024

    2024

  5. [13]

    Collab- orative inference via dynamic composition of tiny ai accelerators on mcus

    Taesik Gong, Si Young Jang, Utku Günay Acer, Fahim Kawsar, and Chulhong Min. Collab- orative inference via dynamic composition of tiny ai accelerators on mcus. arXiv preprint arXiv:2401.08637, 2023

    2023 arXiv

  6. [14]

    Caltech-256 object category dataset

    Gregory Griffin, Alex Holub, and Pietro Perona. Caltech-256 object category dataset. 2007

    2007

  7. [15]

    Deep compression: Compressing deep neural networks with pruning, trained quantization and huffman coding

    Song Han, Huizi Mao, and William J Dally. Deep compression: Compressing deep neural networks with pruning, trained quantization and huffman coding. International Conference on Learning Representations (ICLR), 2016

    2016

  8. [16]

    Lets keep it simple, using simple architectures to outperform deeper and more complex archi- tectures

    Seyyed Hossein Hasanpour, Mohammad Rouhani, Mohsen Fayyaz, and Mohammad Sabokrou. Lets keep it simple, using simple architectures to outperform deeper and more complex archi- tectures. arXiv preprint arXiv:1608.06037, 2016

    2016 arXiv

  9. [17]

    Channel pruning for accelerating very deep neural networks

    Yihui He, Xiangyu Zhang, and Jian Sun. Channel pruning for accelerating very deep neural networks. In Proceedings of the IEEE international conference on computer vision , pages 1389–1397, 2017. 11

    2017

  10. [18]

    Imagenette

    Jeremy Howard. Imagenette. https://github.com/fastai/imagenette/. Accessed: 20 May. 2024

    2024

  11. [19]

    Ai8x synthesis repository

    Analog Devices Inc. Ai8x synthesis repository. https://github.com/analogdevicesinc/ ai8x-synthesis, 2024. Accessed: 20 May. 2024

    2024

  12. [20]

    Ai8x training repository

    Analog Devices Inc. Ai8x training repository. https://github.com/analogdevicesinc/ ai8x-training, 2024. Accessed: 20 May. 2024

    2024

  13. [21]

    Quantization and training of neural networks for efficient integer-arithmetic-only inference

    Benoit Jacob, Skirmantas Kligys, Bo Chen, Menglong Zhu, Matthew Tang, Andrew Howard, Hartwig Adam, and Dmitry Kalenichenko. Quantization and training of neural networks for efficient integer-arithmetic-only inference. In Proceedings of the IEEE conference on computer vision an...

    2018

  14. [22]

    Adam: A method for stochastic optimization

    Diederik Kingma and Jimmy Ba. Adam: A method for stochastic optimization. In International Conference on Learning Representations (ICLR), San Diega, CA, USA, 2015

    2015

  15. [23]

    Tinytrain: Deep neural network training at the extreme edge

    Young D Kwon, Rui Li, Stylianos I Venieris, Jagmohan Chauhan, Nicholas D Lane, and Cecilia Mascolo. Tinytrain: Deep neural network training at the extreme edge. arXiv preprint arXiv:2307.09988, 2023

    2023 arXiv

  16. [24]

    µnas: Constrained neural architecture search for microcontrollers

    Edgar Liberis, Łukasz Dudziak, and Nicholas D Lane. µnas: Constrained neural architecture search for microcontrollers. In Proceedings of the 1st Workshop on Machine Learning and Systems, pages 70–79, 2021

    2021

  17. [25]

    Differentiable neural network pruning to enable smart applications on microcontrollers

    Edgar Liberis and Nicholas D Lane. Differentiable neural network pruning to enable smart applications on microcontrollers. Proceedings of the ACM on Interactive, Mobile, Wearable and Ubiquitous Technologies, 6(4):1–19, 2023

    2023

  18. [26]

    Mcunetv2: Memory-efficient patch-based inference for tiny deep learning

    Ji Lin, Wei-Ming Chen, Han Cai, Chuang Gan, and Song Han. Mcunetv2: Memory-efficient patch-based inference for tiny deep learning. arXiv preprint arXiv:2110.15352, 2021

    2021 arXiv

  19. [27]

    Runtime neural pruning

    Ji Lin, Yongming Rao, Jiwen Lu, and Jie Zhou. Runtime neural pruning. Advances in neural information processing systems, 30, 2017

    2017

  20. [28]

    On- device training under 256kb memory

    Ji Lin, Ligeng Zhu, Wei-Ming Chen, Wei-Chen Wang, Chuang Gan, and Song Han. On- device training under 256kb memory. Advances in Neural Information Processing Systems, 35:22941–22954, 2022

    2022

  21. [29]

    An intriguing failing of convolutional neural networks and the coordconv solution

    Rosanne Liu, Joel Lehman, Piero Molino, Felipe Petroski Such, Eric Frank, Alex Sergeev, and Jason Yosinski. An intriguing failing of convolutional neural networks and the coordconv solution. Advances in neural information processing systems, 31, 2018

    2018

  22. [30]

    Multi-channel cnn-based object detection for enhanced situation awareness

    Shuo Liu and Zheng Liu. Multi-channel cnn-based object detection for enhanced situation awareness. arXiv preprint arXiv:1712.00075, 2017

    2017 arXiv

  23. [31]

    Metapruning: Meta learning for automatic neural network channel pruning

    Zechun Liu, Haoyuan Mu, Xiangyu Zhang, Zichao Guo, Xin Yang, Kwang-Ting Cheng, and Jian Sun. Metapruning: Meta learning for automatic neural network channel pruning. In Proceedings of the IEEE/CVF international conference on computer vision, pages 3296–3305, 2019

    2019

  24. [32]

    Learning efficient convolutional networks through network slimming

    Zhuang Liu, Jianguo Li, Zhiqiang Shen, Gao Huang, Shoumeng Yan, and Changshui Zhang. Learning efficient convolutional networks through network slimming. In Proceedings of the IEEE international conference on computer vision, pages 2736–2744, 2017

    2017

  25. [33]

    https://www.analog.com/en/products/max32650.html

    Analog MAX32650. https://www.analog.com/en/products/max32650.html. Ac- cessed: 20 May. 2024

    2024

  26. [34]

    https://www.analog.com/en/products/max78000.html

    Analog MAX78000. https://www.analog.com/en/products/max78000.html. Ac- cessed: 20 May. 2024

    2024

  27. [35]

    https: //cms.tinyml.org/wp-content/uploads/talks2020/tinyML_Talks_Kris_Ardis_ and_Robert_Muchsel_-201027.pdf

    Cutting the AI Power Cord: Technology to Enable True Edge Inference. https: //cms.tinyml.org/wp-content/uploads/talks2020/tinyML_Talks_Kris_Ardis_ and_Robert_Muchsel_-201027.pdf. Accessed: 20 May. 2024. 12

    2024

  28. [36]

    https://www.analog.com/en/design-center/ evaluation-hardware-and-software/evaluation-boards-kits/max78000fthr

    Analog MAX78000FTHR. https://www.analog.com/en/design-center/ evaluation-hardware-and-software/evaluation-boards-kits/max78000fthr. html. Accessed: 20 May. 2024

    2024

  29. [37]

    https://www.analog.com/en/products/max78002.html

    Analog MAX78002. https://www.analog.com/en/products/max78002.html. Ac- cessed: 20 May. 2024

    2024

  30. [38]

    https://www.analog.com/en/design-center/ evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit

    Analog MAX78002EVKIT. https://www.analog.com/en/design-center/ evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit. html. Accessed: 20 May. 2024

    2024

  31. [39]

    Tinyissimoyolo: A quantized, low-memory footprint, tinyml object detection network for low power microcon- trollers

    Julian Moosmann, Marco Giordano, Christian V ogt, and Michele Magno. Tinyissimoyolo: A quantized, low-memory footprint, tinyml object detection network for low power microcon- trollers. In 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (...

    2023

  32. [40]

    Ultra-low power dnn accelerators for iot: Resource characterization of the max78000

    Arthur Moss, Hyunjong Lee, Lei Xun, Chulhong Min, Fahim Kawsar, and Alessandro Mon- tanari. Ultra-low power dnn accelerators for iot: Resource characterization of the max78000. In Proceedings of the 20th ACM Conference on Embedded Networked Sensor Systems, pages 934–940, 2022

    2022

  33. [41]

    Pytorch: An imperative style, high-performance deep learning library

    Adam Paszke, Sam Gross, Francisco Massa, Adam Lerer, James Bradbury, Gregory Chanan, Trevor Killeen, Zeming Lin, Natalia Gimelshein, Luca Antiga, et al. Pytorch: An imperative style, high-performance deep learning library. Advances in neural information processing systems, 32, 2019

    2019

  34. [42]

    Xnor-net: Imagenet classification using binary convolutional neural networks

    Mohammad Rastegari, Vicente Ordonez, Joseph Redmon, and Ali Farhadi. Xnor-net: Imagenet classification using binary convolutional neural networks. In European conference on computer vision, pages 525–542. Springer, 2016

    2016

  35. [43]

    Kp2dtiny: Quantized neural keypoint detection and description on the edge

    Thomas Rüegg, Marco Giordano, and Michele Magno. Kp2dtiny: Quantized neural keypoint detection and description on the edge. In 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), pages 1–5. IEEE, 2023

    2023

  36. [44]

    Memory-driven mixed low precision quantization for enabling deep network inference on microcontrollers

    Manuele Rusci, Alessandro Capotondi, and Luca Benini. Memory-driven mixed low precision quantization for enabling deep network inference on microcontrollers. Proceedings of Machine Learning and Systems, 2:326–335, 2020

    2020

  37. [45]

    Mobilenetv2: Inverted residuals and linear bottlenecks

    Mark Sandler, Andrew Howard, Menglong Zhu, Andrey Zhmoginov, and Liang-Chieh Chen. Mobilenetv2: Inverted residuals and linear bottlenecks. In Proceedings of the IEEE conference on computer vision and pattern recognition, pages 4510–4520, 2018

    2018

  38. [46]

    Smith, and Oren Etzioni

    Roy Schwartz, Jesse Dodge, Noah A. Smith, and Oren Etzioni. Green ai. Commun. ACM, 63(12):54–63, nov 2020

    2020

  39. [47]

    https://www.st.com/en/microcontrollers-microprocessors/ stm32f7-series.html

    STM32F7 Series. https://www.st.com/en/microcontrollers-microprocessors/ stm32f7-series.html. Accessed: 20 May. 2024

    2024

  40. [48]

    Efficientnetv2: Smaller models and faster training

    Mingxing Tan and Quoc Le. Efficientnetv2: Smaller models and faster training. InInternational conference on machine learning, pages 10096–10106. PMLR, 2021

    2021

  41. [49]

    Haq: Hardware-aware automated quantization with mixed precision

    Kuan Wang, Zhijian Liu, Yujun Lin, Ji Lin, and Song Han. Haq: Hardware-aware automated quantization with mixed precision. In Proceedings of the IEEE/CVF conference on computer vision and pattern recognition, pages 8612–8620, 2019

    2019

  42. [50]

    Depth-aware cnn for rgb-d segmentation

    Weiyue Wang and Ulrich Neumann. Depth-aware cnn for rgb-d segmentation. In Proceedings of the European conference on computer vision (ECCV), pages 135–150, 2018

    2018

  43. [51]

    Location augmentation for cnn

    Zhenyi Wang and Olga Veksler. Location augmentation for cnn. arXiv preprint arXiv:1807.07044, 2018

    2018 arXiv

  44. [52]

    Streamnet: Memory- efficient streaming tiny deep learning inference on the microcontroller

    Hong-Sheng Zheng, Yu-Yuan Liu, Chen-Fong Hsu, and Tsung Tai Yeh. Streamnet: Memory- efficient streaming tiny deep learning inference on the microcontroller. Advances in Neural Information Processing Systems, 36, 2024. 13

    2024

  45. [53]

    Dorefa-net: Training low bitwidth convolutional neural networks with low bitwidth gradients.arXiv preprint arXiv:1606.06160, 2016

    Shuchang Zhou, Yuxin Wu, Zekun Ni, Xinyu Zhou, He Wen, and Yuheng Zou. Dorefa-net: Training low bitwidth convolutional neural networks with low bitwidth gradients.arXiv preprint arXiv:1606.06160, 2016

    2016 arXiv

  46. [54]

    [Yes] " is generally preferable to

    Chenzhuo Zhu, Song Han, Huizi Mao, and William J Dally. Trained ternary quantization. In International Conference on Learning Representations, 2016. 14 A Experimental details For all experiments conducted in the paper, we used three different random seeds (0, 1, 2) and reporte...

    2016

  47. [55]

    Guidelines: • The answer NA means that the abstract and introduction do not include the claims made in the paper

    Claims Question: Do the main claims made in the abstract and introduction accurately reflect the paper’s contributions and scope? Answer: [Yes] Justification: The main claims in the abstract and introduction accurately reflect the paper’s contributions and scope. Guidelines: •...

  48. [56]

    Limitations

    Limitations Question: Does the paper discuss the limitations of the work performed by the authors? Answer: [Yes] 21 Justification: See §6. Guidelines: • The answer NA means that the paper has no limitation while the answer No means that the paper has limitations, but those are...

  49. [57]

    Guidelines: • The answer NA means that the paper does not include theoretical results

    Theory Assumptions and Proofs Question: For each theoretical result, does the paper provide the full set of assumptions and a complete (and correct) proof? Answer: [NA] Justification: No theoretical result. Guidelines: • The answer NA means that the paper does not include theo...

  50. [58]

    Guidelines: • The answer NA means that the paper does not include experiments

    Experimental Result Reproducibility Question: Does the paper fully disclose all the information needed to reproduce the main ex- perimental results of the paper to the extent that it affects the main claims and/or conclusions of the paper (regardless of whether the code and da...

  51. [59]

    Guidelines: • The answer NA means that paper does not include experiments requiring code

    Open access to data and code Question: Does the paper provide open access to the data and code, with sufficient instruc- tions to faithfully reproduce the main experimental results, as described in supplemental material? Answer: [Yes] Justification: Yes, the source code is ava...

  52. [60]

    Guidelines: • The answer NA means that the paper does not include experiments

    Experimental Setting/Details Question: Does the paper specify all the training and test details (e.g., data splits, hyper- parameters, how they were chosen, type of optimizer, etc.) necessary to understand the results? Answer: [Yes] Justification: Experimental details are in §...

  53. [61]

    We ran the experiments with three random seems (0,1,2) and reported the standard deviations

    Experiment Statistical Significance Question: Does the paper report error bars suitably and correctly defined or other appropriate information about the statistical significance of the experiments? Answer: [Yes] Justification: See 4.2. We ran the experiments with three random ...

  54. [62]

    Guidelines: • The answer NA means that the paper does not include experiments

    Experiments Compute Resources Question: For each experiment, does the paper provide sufficient information on the com- puter resources (type of compute workers, memory, time of execution) needed to reproduce the experiments? Answer: [Yes] Justification: See §2, §4, and Appendi...

  55. [63]

    Guidelines: • The answer NA means that the authors have not reviewed the NeurIPS Code of Ethics

    Code Of Ethics Question: Does the research conducted in the paper conform, in every respect, with the NeurIPS Code of Ethics https://neurips.cc/public/EthicsGuidelines? Answer: [Yes] Justification: We follow the NeurIPS Code of Ethics. Guidelines: • The answer NA means that th...

  56. [64]

    Guidelines: • The answer NA means that there is no societal impact of the work performed

    Broader Impacts Question: Does the paper discuss both potential positive societal impacts and negative societal impacts of the work performed? Answer: [Yes] Justification: See §6. Guidelines: • The answer NA means that there is no societal impact of the work performed. • If th...

  57. [65]

    Guidelines: • The answer NA means that the paper poses no such risks

    Safeguards Question: Does the paper describe safeguards that have been put in place for responsible release of data or models that have a high risk for misuse (e.g., pretrained language models, image generators, or scraped datasets)? Answer: [NA] Justification: No such compone...

  58. [66]

    Guidelines: • The answer NA means that the paper does not use existing assets

    Licenses for existing assets Question: Are the creators or original owners of assets (e.g., code, data, models), used in the paper, properly credited and are the license and terms of use explicitly mentioned and properly respected? Answer: [Yes] Justification: See §4 and Appen...

  59. [67]

    Guidelines: • The answer NA means that the paper does not release new assets

    New Assets Question: Are new assets introduced in the paper well documented and is the documentation provided alongside the assets? Answer: [NA] Justification: No new assets. Guidelines: • The answer NA means that the paper does not release new assets. • Researchers should com...

  60. [68]

    26 Guidelines: • The answer NA means that the paper does not involve crowdsourcing nor research with human subjects

    Crowdsourcing and Research with Human Subjects Question: For crowdsourcing experiments and research with human subjects, does the paper include the full text of instructions given to participants and screenshots, if applicable, as well as details about compensation (if any)? A...

  61. [69]

    Guidelines: • The answer NA means that the paper does not involve crowdsourcing nor research with human subjects

    Institutional Review Board (IRB) Approvals or Equivalent for Research with Human Subjects Question: Does the paper describe potential risks incurred by study participants, whether such risks were disclosed to the subjects, and whether Institutional Review Board (IRB) approvals...

Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.