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REVIEW 3 major objections 6 minor 71 references

AC/DC: Automated Compilation for Dynamic Circuits

T0 review · 3 major / 6 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read The paper presents an automated framework that synthesizes dynamic quantum circuits—circuits with mid-circuit measurements and feed-forward operations—to prepare arbitrary quantum states or implement arbitrary unitary operators, using…

desk verdict Useful synthesis framework and honest hardware study; the 'any' claim outruns the implemented U3-only branch ansatz. read the letter →

arxiv 2412.07969 v1 pith:P2N4F7I3 submitted 2024-12-10 quant-ph

Siyuan Niu , Efekan Kokcu , Anupam Mitra , Aaron Szasz , Akel Hashim , Justin Kalloor , Wibe Albert de Jong , Costin Iancu
show 1 more author
Ed Younis
This is my paper · ORCID
classification quant-ph MSC 81P68 PACS 03.67.Lx
keywords dynamicquantumcircuitsmid-circuitmeasurementfeed-forwardcircuitsynthesisnumericaloptimizationstatepreparationunitarycostfunction
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Dynamic quantum circuits—circuits that measure some qubits mid-execution and choose later gates based on the outcome—have so far been hand-designed, mostly from teleportation protocols. This paper claims to replace that manual design with numerical optimization: given a target state or unitary, a search routine finds a circuit of the form "prepare with $U_b$, measure ancillas, then apply branch unitary $U_i$ depending on outcome" that realizes the target. The paper introduces two families of cost functions, one for state preparation and one for unitary preparation, and proves they are faithful. It implements these in an open-source synthesis framework and shows the resulting dynamic circuits match or beat static circuits in depth across GHZ, W, and Dicke states, long-range entangling gates, multi-qubit gates, block-level optimization of quantum algorithms, and lattice simulations. Hardware and noisy-simulation validation show the depth savings are real but currently offset by mid-circuit measurement errors; the paper's noise model quantifies the measurement fidelity needed for dynamic circuits to win.

What carries the argument

The mechanism is the branched circuit identity $U = \sum_i (U_i \otimes |i\rangle\langle i|) U_b$, interpreting the measurement as a projection-valued decomposition of the ancilla. The new cost functions turn the non-unitary measurement process into an objective a numerical optimizer can drive to zero: for unitary preparation the key trick is deferring the measurement, so the task becomes making the pre-measurement unitary $U$ equal to $V\otimes W$ on the ancilla-zero subspace, and $C_{\mathrm{dyn1}}$ and $C_{\mathrm{dyn2}}$ are the resulting Hilbert-Schmidt distances. Type 2 is also derived independently from a quantum-channel composition, giving it an operational meaning as the trace of the channel implementing $V^\dagger$ after the dynamic circuit. The implementation combines a topology-aware search for the pre-measurement block with instantiation of one layer of single-qubit $U_3$ gates per branch, and the paper documents circuit patterns for GHZ, W, Dicke, long-range gates, and Trotter steps that allow scaling via fixed-layer growth or circuit partitioning.

What would settle it

Run the generator on a Haar-random three-qubit unitary with one ancilla and compare the optimized cost under the single-U3-layer branch restriction against a version that allows two-qubit gates in branches; if the restricted version cannot reach the same near-zero cost that the unrestricted version reaches, the expressiveness assumption underlying "any unitary" is false.

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Extended reading notes

Core claim

Dynamic circuits have mostly been designed by hand using teleportation and stabilizer reasoning. The paper's central claim is that they can instead be found automatically: for a target state or unitary, search over a pre-measurement unitary $U_b$ on system-plus-ancilla qubits and over outcome-conditioned branch unitaries $U_i$, guided by cost functions that are faithful—zero exactly when the circuit realizes the target. For state preparation the cost is $C_T = 1 - \sum_i |\langle T \otimes i| (U_i \otimes |i\rangle\langle i|) U_b |0^{\otimes(s+a)}\rangle|^2$. For unitary preparation, the paper defers the measurement and demands the pre-measurement state factorize as $(V|\phi\rangle)\otimes|\alpha\rangle$, yielding two costs: $C_{\mathrm{dyn1}}$ with an extra ancilla unitary $W$, and $C_{\mathrm{dyn2}}$ with $W$ optimized away, $C_{\mathrm{dyn2}}(U)=1-\frac{1}{4^s}\sum_i |\mathrm{Tr}(V^\dagger U_{i,0})|^2$, where $U_{i,0}$ is a partial trace over ancillas. The same costs extend to independent and nested measurement placements by changing the form of the total unitary $U$. The implementation uses a topology-aware search for $U_b$ and one layer of single-qubit $U_3$ gates per branch; on the demonstrated targets the resulting circuits are shallower than static-circuit baselines, and hardware validation confirms the protocol works, with fidelity currently limited by mid-circuit measurement errors.

Load-bearing premise

The generated circuits only allow a single layer of single-qubit U3 gates in each branch after the measurement, and the paper does not prove that this restricted branch ansatz can prepare every state or unitary; if some targets require entangled or deeper branch unitaries, the "any target" claim would fail as implemented.

Editorial extensions

If this is right

  • For GHZ and W states, dynamic circuits reach depth 2–4 for up to 8 qubits, shallower than analytic or compiled static circuits, with depth growing more slowly with qubit count.
  • Long-range two-qubit gates such as CNOT, CZ, CS, Rzz, Rxx, and Ryy are realized in constant depth, with specific gates at depth 2 and generic two-qubit gates at depth 6, using one measurement per skipped qubit and cutting the number of mid-circuit measurements by a factor of three relative to Bell-state teleportation.
  • Partitioning large algorithms into three-qubit blocks and replacing blocks with one-ancilla dynamic circuits reduces circuit depth by about 30% on Grover, TFIM, and QAOA circuits at the cost of about 13% more CNOTs, with a mixed static/dynamic choice recovering the CNOT overhead.
  • For lattice-simulation Trotter steps mapped to limited-connectivity hardware, dynamic long-range Rzz circuits halve the CNOT count relative to structure-aware unitary synthesis, at constant circuit depth.
  • The noise model predicts a threshold mid-circuit measurement fidelity above which dynamic circuits beat static ones; the threshold drops as circuit width grows, and for lattice simulation it is already below current readout fidelity under the model's assumptions.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • An implication the authors leave implicit is that allowing two-qubit gates inside branch unitaries—not just one layer of single-qubit U3 gates—would likely reduce depth further, since the cost functions themselves do not constrain branch structure; the paper flags this as future work rather than claiming it.
  • If mid-circuit measurement fidelity reaches the thresholds their model computes, dynamic-circuit synthesis becomes a general depth-reduction tool for NISQ algorithms, not just for the demonstrated families; this is an extrapolation from the paper's trade-off curves.
  • The same generator could be used to build algorithm-level hardware benchmarks for mid-circuit measurement and feed-forward, since it produces many circuits with tunable depth, width, and measurement trade-offs; the paper mentions benchmarks as a motivation but does not build the suite.
  • The constant-depth long-range gate pattern suggests the technique extends naturally to distributing entanglement across arbitrary pairs in limited-connectivity processors, potentially aiding distributed quantum computing; the paper only demonstrates linear topologies.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The paper presents AC/DC, a framework for automatically synthesizing dynamic quantum circuits that include mid-circuit measurements and classical feed-forward. The authors derive cost functions for state preparation (Eq. 6) and unitary preparation (Cdyn1, Eq. 9; Cdyn2, Eq. 10), prove their faithfulness in Appendices A-C, and integrate them into the open-source BQSKit synthesis toolkit via two algorithms, DC-QSearch and DC-Inst. They demonstrate the framework on GHZ, W, and Dicke state preparation; long-range entangling gates; multi-qubit gates; large-circuit optimization through partitioning; and a lattice-simulation application, with validation on simulators and quantum hardware. They also present a noise model analyzing when dynamic circuits can outperform unitary circuits.

Significance. If the results hold, this is a valuable step toward practical automated compilation for dynamic circuits. The cost functions are derived from first principles, and the faithfulness proofs in Appendices A-C are rigorous and reusable beyond the specific BQSKit implementation. The integration into an open-source framework, the hardware validation, and the noise trade-off analysis are concrete strengths that will benefit the community. The main caveat is that the headline claim of preparing 'any state or unitary operator' is not supported by the implemented generator as described; the implemented branch unitaries are restricted to single-qubit layers, and the large-circuit scaling claims rest on pattern extrapolation rather than direct synthesis. These issues are fixable with qualified claims and additional evidence, but they affect the central assertion of the paper.

major comments (3)
  1. [Abstract and Section VI] The abstract's claim that the framework can 'automatically prepare any state or unitary operator' is not supported by the implemented generator. Section VI restricts every branch unitary Ui to a single layer of single-qubit U3 gates, and Section VIII explicitly acknowledges that allowing entangled branch unitaries 'might further reduce the circuit depth' and that simultaneous synthesis of Ub and all Ui is left to future work. The paper proves faithfulness of the cost functions but does not prove that a zero-cost solution exists within this restricted ansatz for an arbitrary target, nor does it provide a convergence guarantee for the numerical search. All demonstrations use structured, symmetric targets; no random dense state or unitary is tested. The claim should be qualified to 'for the demonstrated targets, and in principle for arbitrary targets given sufficient search depth and more general branch unitaries,' or supplemented with a completeness argument for the implemented ansatz.
  2. [Section IV, Eq. (12)] The uniform-measurement restriction W = D H^{⊗n} is introduced as an 'empirical observation' and then used as an assumption in the type-1 cost function. This restriction may change the optimization landscape: a zero-cost solution may exist for the full W but not within the D H^{⊗n} family, so Cdyn1 with this restricted W is not proven faithful to the original dynamic-circuit problem. The paper does not show that uniform measurement probabilities are without loss of optimality for general targets; Figure 3 illustrates only a single next-nearest-neighbor CNOT. This should be stated as a heuristic with a discussion of its possible impact on completeness, or removed by optimizing W analytically as in Cdyn2.
  3. [Section VII A and Figure 10] Large-circuit results are obtained by DC-Inst, which extrapolates a pattern observed on circuits with at most six qubits, and Figure 10 explicitly labels the large-size depth curves as 'predictions derived from observed patterns.' Tables I and II report GHZ7/GHZ8 and W6 results from this extrapolation, but no direct synthesis or hardware validation is provided for those sizes. The scaling claims should be clearly labeled as extrapolations, and ideally validated by at least one intermediate-size directly synthesized circuit or by executing the predicted circuit on a simulator.
minor comments (6)
  1. [Section VI] There is a typo in 'allows us to reproduce all previosuly dynamic circuit published results'; 'previosuly' should be 'previously.'
  2. [Table III caption] The caption contains the typo 'DC achievs the shortest circuit depth'; 'achievs' should be 'achieves.'
  3. [Equation (19) and Figure 5] The text states that 'Each blue block is explained in Eq. (19),' but Eq. (19) is empty in the manuscript; the block's unitary decomposition (one CNOT plus two U3 gates) should be written explicitly.
  4. [Section V, Eq. (15)] The unitaries Ub0 and Ub1 used in the independent-measurement expression are not defined; please define them or relate them to the general Ub notation used elsewhere.
  5. [Appendix B] The equivalence argument between Cdyn1 and Cdyn2 would be clearer if it stated the monotonic relation Cdyn2 = 1 - (1 - Cdyn1)^2, which makes the optimization equivalence immediate; as written, 'both are aiming to maximize |T|' is somewhat informal.
  6. [Appendix D, Figure 15] The caption panel labels are inconsistent: panel (c) is described as 'CNOT between (q0, q3),' but the figure appears to show a three-qubit circuit; please reconcile the labels and the described gates.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: cost functions are derived and proved from first principles; extrapolated patterns are labeled heuristics, not fitted predictions.

full rationale

The paper's central derivation is self-contained. The state-preparation cost CT (Eq. 6) is derived from fidelity and proved faithful in Appendix A; the unitary-preparation costs Cdyn1 and Cdyn2 (Eqs. 9 and 10) are derived from the Hilbert-Schmidt/subspace fidelity and proved faithful in Appendix B, with an independent channel-theoretic derivation in Appendix C. These proofs do not assume the target result, and no fitted parameter is renamed as a prediction. The uniform-outcome assumption Eq. (12) is an empirical simplification that reduces the number of W parameters, but it is not derived from the target and does not define the cost functions; the paper explicitly presents it as an observed pattern, with Figure 3 as supporting evidence. The DC-Inst large-circuit depth predictions (e.g., Figure 10) are explicitly labeled as 'predictions derived from observed patterns,' and Section VI describes a prescribed circuit-extension methodology rather than a fitted-input-called-prediction loop; this is a heuristic extrapolation, a correctness/completeness concern, not circularity. Self-citations to BQSKit, QSearch, and related tools are tool citations and performance comparisons, not load-bearing substitutes for the derived objectives or their faithfulness proofs. The abstract's 'any state or unitary' claim is indeed stronger than what the implemented U3-only branch ansatz is proven to achieve, and Section VIII acknowledges that entangled branch unitaries could further reduce depth; however, that is a completeness/expressivity gap, not an exhibited equation reducing to its own input. No step was found in which a claimed prediction is equivalent by construction to a fitted parameter or to a self-citation chain.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

The central claim rests on standard synthesis assumptions plus two ad hoc structural ansatze: the U3-only branch unitaries and the uniform-outcome W restriction. These are not proven from first principles and bound the generality of the 'any state or unitary' claim.

assumptions (5)
  • ad hoc to paper A single layer of single-qubit U3 gates per branch is expressive enough to prepare any target state or unitary when combined with a suitable Ub.
    Section VI restricts each Ui to one layer of U3 gates; the paper claims this reproduces all previously published dynamic circuit results, but no expressiveness proof is given, while the abstract claims preparation of any state or unitary.
  • ad hoc to paper Optimal circuits always have uniform measurement outcome distribution, so W can be restricted to W = D H⊗n.
    Section IV, Eq. (12) and Figure 3: an empirical observation, not proven, used to reduce the number of parameters in Cdyn1.
  • domain assumption Deferring mid-circuit measurements to the end of the circuit is valid for deriving cost functions.
    Section IV, Figure 2(b): the derivation assumes ancilla qubits are not reused before the final measurement, standard in dynamic circuit analysis.
  • domain assumption The noise model in Eq. (26) assumes mid-circuit measurement errors affect all qubits equally (factor N).
    Section VII E: used to compute the MCM fidelity threshold; the authors note this is a worst-case assumption.
  • standard math Eigenvalue characterization of quantum channels (all eigenvalues +1 if and only if identity channel), cited from [54,55].
    Appendix C uses this to show the trace-based cost function is faithful.

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Cite this review

Pith. "Pith review of AC/DC: Automated Compilation for Dynamic Circuits." pith.science (2026). https://pith.science/paper/P2N4F7I3

@misc{pith2026241207969,
  author       = {Pith},
  title        = {Pith review of: AC/DC: Automated Compilation for Dynamic Circuits},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/P2N4F7I3}},
  note         = {Machine review of arXiv:2412.07969}
}
read the original abstract

Dynamic quantum circuits incorporate mid-circuit measurements and feed-forward operations originally intended to realize Quantum Error Correction. This paradigm has recently been utilized to prepare certain states and long-range entangling gates as well as reduce resource overhead in quantum algorithms such as Quantum Fourier Transformation and Quantum Phase Estimation. In this paper, we present a novel framework for generating dynamic quantum circuits that automatically prepare any state or unitary operator. This procedure is powered by numerical optimization-based circuit synthesis methods. The first contribution is introducing optimization objective functions incorporating mid-circuit measurement and feed-forward operations. The second contribution is incorporating these into a popular open-source quantum circuit synthesis framework. We demonstrate the generation of dynamic circuits for state preparation, long-range entangling gates, circuit optimization, and the application of dynamic circuits to lattice simulations. The resulting circuits are validated through simulation and execution on quantum hardware. Furthermore, we perform noise analysis to explore the impact of different error ratios in mid-circuit measurements and gate errors, identifying scenarios where dynamic circuits offer the most significant benefits. The dynamic circuits generated by our framework show substantial improvements in reducing circuit depth and, in some cases, the number of gates required. To our knowledge, this is the first practical procedure to generate dynamic quantum circuits. Our objective functions are independent of the underlying synthesis framework and can be easily reused. This framework opens new possibilities for circuit generation and optimization methods, highlighting the potential of dynamic circuits to enhance the performance of quantum algorithms on near-term quantum computers.

Figures

Figures reproduced from arXiv: 2412.07969 by the authors.

Figure 1
Figure 1. FIG. 1: Dynamic circuit protocol for preparing a target [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. FIG. 2: Panel (a) is the dynamic circuit protocol for [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. FIG. 3: The effect of setting the measurement proba [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (12 more)
Figure 4
Figure 4. Figure 4: FIG. 4: Circuits with two ancillas to illustrate different mid-circuit measurement scenarios. (a) Measurement of [PITH_FULL_IMAGE:figures/full_fig_p006_4.png]
Figure 5
Figure 5. Figure 5: FIG. 5: The circuit structures to prepare [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]
Figure 6
Figure 6. Figure 6: FIG. 6: The circuit structures to prepare [PITH_FULL_IMAGE:figures/full_fig_p010_6.png]
Figure 7
Figure 7. Figure 7: FIG. 7: Output distribution of the state preparation circuits for (a) GHZ [PITH_FULL_IMAGE:figures/full_fig_p010_7.png]
Figure 8
Figure 8. Figure 8: FIG. 8: The TVD results for executing unitary and dynamic circuits to prepare various quantum states on (a) noise [PITH_FULL_IMAGE:figures/full_fig_p011_8.png]
Figure 9
Figure 9. Figure 9: FIG. 9: The circuit structures to prepare [PITH_FULL_IMAGE:figures/full_fig_p011_9.png]
Figure 10
Figure 10. Figure 10: FIG. 10: The predicted circuit depth of long-range [PITH_FULL_IMAGE:figures/full_fig_p012_10.png]
Figure 11
Figure 11. Figure 11: FIG. 11: The fidelity results for executing unitary and dynamic circuits to prepare long-range CNOT gate on linear [PITH_FULL_IMAGE:figures/full_fig_p013_11.png]
Figure 12
Figure 12. Figure 12: FIG. 12: On panel [PITH_FULL_IMAGE:figures/full_fig_p015_12.png]
Figure 13
Figure 13. Figure 13: FIG. 13: Number of CNOTs when mapping the [PITH_FULL_IMAGE:figures/full_fig_p015_13.png]
Figure 14
Figure 14. Figure 14: FIG. 14: The mid-circuit measurement (MCM) fidelity required for dynamic circuits to outperform unitary circuits [PITH_FULL_IMAGE:figures/full_fig_p016_14.png]
Figure 15
Figure 15. Figure 15: FIG. 15: Dynamic circuits for preparing (a) W3 state on ( [PITH_FULL_IMAGE:figures/full_fig_p024_15.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

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