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Evaluating the performance of quantum processing units at large width and depth

T0 review · 4 major / 4 minor · reviewed 2026-08-08 · deepseek-v4-flash

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Pith's one-line read A single fixed-parameter quantum algorithm can rank processors by the depth at which they lose their algorithmic signal, a benchmark the authors apply to 24 QPUs.

desk verdict Broad, open QPU benchmark with real data and a clear pass/fail protocol; the per-backend parameter schedule and best-section selection undercut the 'architecture-neutral' claim but don't sink the main trends. read the letter →

arxiv 2502.06471 v2 pith:BAZIRMYC submitted 2025-02-10 quant-ph

J. A. Montanez-Barrera , Kristel Michielsen , David E. Bernal Neira This is my paper · ORCID
classification quant-ph PACS 03.67.Lx
keywords quantumbenchmarkingLR-QAOAapproximationratioWeightedMaxCutcross-platformcomparisonfractionalgateserrorperlayeredgatevolume
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that a deliberately simple, fixed-parameter version of QAOA, called linear-ramp QAOA (LR-QAOA), can serve as a scalable, architecture-neutral benchmark for quantum processors, and it tests that claim on 24 devices from six vendors. The benchmark asks one question: as circuit depth grows, does the processor's output stay statistically better than random sampling? A device passes at a given depth if its approximation ratio exceeds a 99.73% confidence threshold set by a random sampler. Applied to Weighted MaxCut problems with up to 156 qubits and 10,000 layers, the protocol produces a concrete performance map: IBM Heron devices outlast Eagle-generation devices in depth scaling, fractional gates halve the two-qubit cost, and Quantinuum's H2-1 is the only platform that passes the 56-qubit fully-connected test. The reason to care is that existing metrics such as quantum volume and error-per-layered-gate do not track algorithmic performance at scale, so there is no agreed way to compare heterogeneous QPUs on realistic, deep workloads.

What carries the argument

The load-bearing object is LR-QAOA, a fixed-parameter variant of QAOA in which the variational search is replaced by a deterministic linear ramp: $\beta_k = (1 - k/p)\Delta_{\beta}$ and $\gamma_k = (k+1)/p\,\Delta_{\gamma}$. The circuit alternates problem and mixer unitaries over $p$ layers, and the performance metric is the approximation ratio $r$ relative to the optimal Weighted MaxCut value, compared with a 99.73% random-sampler confidence interval through the normalized effective ratio $r_{\rm eff}$. Because the schedule is fixed, circuits can be generated identically on any device, scaled in width and depth, and mapped onto 1D-chain, native-layout, and fully-connected topologies; the random threshold turns a noisy signal into a binary pass/fail test of coherent algorithmic signal.

What would settle it

Re-run the 56-qubit fully-connected benchmark on Quantinuum H2-1 after a fresh calibration using 100 samples instead of 7; if the approximation ratio falls inside the random-sampler 99.73% interval, the claimed certification was a statistical or calibration artifact.

Watch

Extended reading notes

Core claim

On the authors' terms, the central discovery is that a non-variational, depth-scaled QAOA schedule gives a reliable probe of a QPU's coherent signal: the approximation ratio rises with depth under ideal evolution and falls into a noise-dominated regime once decoherence takes over, so the depth at which it crosses the random-sampler threshold measures usable circuit depth. Applying this to 24 QPUs gives a concrete ranking. Quantinuum's H2-1 is the only device that passes the fully connected benchmark at 56 qubits, with $r = 0.872$ and $r_{\rm eff} = 0.079$, the largest certified QAOA runs to date, moving past the exact classical simulation threshold near 50 qubits. Among IBM devices, Heron-generation chips outperform Eagle-generation chips in depth scaling, and fractional ZZ gates cut the number of two-qubit operations in half, which the paper identifies as a major reason for the gain. The paper also finds that error-per-layered-gate values do not consistently predict algorithmic performance, and that the benchmark is stable over time (under 1% variation over two months) and remains decisive even with as few as seven measurement samples.

Load-bearing premise

The rankings assume that selecting the best-performing physical qubit section of each device gives a fair basis for comparing whole processors across vendors.

Editorial extensions

If this is right

  • A vendor-neutral, depth-centric benchmark can be standardized for near-term quantum hardware, since LR-QAOA is reproducible, requires no variational optimization, and stays stable over time.
  • Device selection for depth-intensive algorithms can be guided by the depth at which each platform leaves the random-sampler region, rather than by gate-fidelity metrics alone.
  • Fractional two-qubit gates on Heron-class IBM chips halve the two-qubit gate count and circuit depth per layer, giving a concrete hardware-innovation lever that this benchmark detects.
  • The protocol exposes platform-specific bottlenecks: superconducting devices are limited by coherence and crosstalk, while trapped-ion devices are limited by slow gates and lack of parallelism.
  • The 56-qubit H2-1 result crosses the exact-classical-simulation threshold, so the benchmark can certify QAOA runs that are not checkable by exact state-vector simulation.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the section-selection procedure reports only the best-performing physical qubit chain, the cross-platform comparison may overstate whole-device capability; a whole-device or median-section version of the benchmark could rank vendors differently.
  • The random-sampler threshold is algorithm-agnostic enough that the same pass/fail logic could be ported to other fixed-depth coherent algorithms, such as quantum simulation or amplitude estimation, to produce a family of depth benchmarks.
  • Because $r_{\rm eff}$ normalizes by the random baseline, the benchmark could be extended to track how algorithmic signal scales against noise models, potentially predicting when error mitigation becomes necessary before deployment.
  • A functional form for the ramp scale, $\Delta_{\beta,\gamma}(N_q)$, is hinted at but not developed; fitting it empirically could extend the useful depth range of the benchmark across problem sizes.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 4 minor

Summary. The manuscript introduces a benchmarking protocol based on LR-QAOA, a non-variational QAOA variant with linearly ramped parameters. The protocol measures the approximation ratio r as a function of circuit depth p for Weighted MaxCut instances on three graph topologies (1D chain, native layout, fully connected) and declares a pass when r exceeds a 99.73% random-sampler threshold. The authors apply it to 24 QPUs/emulators from six vendors, with up to 156 qubits and p = 10,000, and report a performance map: Heron-class IBM devices outperform Eagle devices, Quantinuum H2-1 is the only platform passing the 56-qubit FC benchmark, EPLG does not predict algorithmic performance, and results are stable over time. The paper includes gate-count formulas, a SWAP-network routing overhead analysis, and raw-data availability on GitHub.

Significance. If the protocol's architecture-neutrality claim can be sustained, this would be a valuable contribution: it is one of the largest cross-platform algorithmic benchmarking studies to date, uses a clearly defined statistical baseline, provides reproducible data, and directly addresses depth scaling rather than gate-level metrics. The honest discussion of sampling effects (Fig. 6) and the explicit statement that parameter values were not tuned per QPU are strengths. However, the central claim is currently compromised by two methodological choices: per-backend Δβ,γ schedules for FC problems (Supplementary Table III) and best-section selection for 1D-chain/FC benchmarks (Supplementary Sec. 4). These need to be reconciled before the benchmark can be called architecture-neutral.

major comments (4)
  1. [Supplementary Sec. 1, Table III; Sec. IV] The FC benchmark uses different Δβ,γ values for different backends for Nq > 15, while Sec. IV states 'For a fair comparison, the same set of parameters must be used across all devices.' Since Supplementary Figs. 8(a), 10(b), and 15 show that r(p) is sensitive to Δβ,γ, and reff in Eq. (8) is computed from rmax, a device evaluated at a favorable Δ (e.g., H2-1 at Δ = 0.2 for Nq = 56) may pass the 99.73% threshold when it would fail at another platform's schedule. The claim that values were 'not tuned for performance on individual QPUs' does not resolve this: the selection still follows a per-backend schedule from the authors' prior work [1], and no robustness test shows that the rankings are invariant to Δ within the range used. Please either run all FC experiments with a common Δ(Nq) schedule, or provide a sensitivity analysis demonstrating that every reported pass/fail decision and ranking is unchanged under the full range of Δ values in Table III.
  2. [Supplementary Sec. 4, Fig. 8(b)-(c)] The 1D-chain and FC benchmarks report the best-performing physical qubit section: 'The section with the highest approximation ratio is highlighted in black... This section selection procedure is used consistently across 1D-chain and FC benchmarks.' This is not equivalent to whole-device performance. The NL benchmark uses all qubits, so cross-benchmark claims such as 'Heron devices outperform Eagle-generation QPUs' and the FC ranking may reflect favorable qubit placement rather than system-wide capability. For FC problems on fixed-layout devices, the SWAP network (Supplementary Sec. 7) maps logical qubits onto a linear chain, so the choice of section directly affects the result; all-to-all trapped-ion devices have no such selection. Please report whole-device (or all-section) results for the 1D-chain and FC benchmarks, or justify why best-section is the appropriate metric for a fair cross-platform comparison.
  3. [Supplementary Sec. 3, Fig. 6; Sec. III.C] The pass criterion uses n = 7 samples for H2-1 at 56 qubits, n = 50/100 for other Quantinuum/IonQ runs, and n = 1000 for IBM devices. Because the random-sampler threshold is rrand = mean + 3σ over subsets of size n, the threshold stringency varies with n (σ scales as 1/sqrt(n)). While the paper correctly notes that smaller samples demand more signal, the cross-platform comparison is not uniform: a device with n = 7 must clear a higher bar than one with n = 1000, and the reported rmax for H2-1 is itself a single 7-sample estimate with large variance. Please either standardize n across devices or show that the qualitative rankings survive when thresholds are computed at a common n.
  4. [Sec. II.A; Sec. IV] The architecture-neutrality of the benchmark rests on the assumption that LR-QAOA's approximation-ratio curve is a faithful, hardware-independent probe of algorithmic signal. The Δ schedule is justified by the same authors' prior work [1] rather than by external or independent validation; no comparison with another fixed-parameter algorithm or a controlled experiment isolating the effect of Δ on the pass/fail decision is provided. This is not a circularity in the measured r values, but it is a correctness risk for the benchmark's validity. Please add a test, e.g., a noiseless simulation across architectures showing that the observed r(p) curves track the known coherent signal, or a comparison with a second fixed-parameter schedule, to support the claim that the protocol measures QPU capability rather than the choice of schedule.
minor comments (4)
  1. [Table II; Sec. III.C] Table II lists reff = 0.020 for ibm fez at Nq = 20, while Sec. III.C reports reff = 0.018 for the same quantity; similarly, H2-1's 56-qubit reff is 0.082 in Table II and 0.079 in the text. Please reconcile these values.
  2. [Throughout] There are several typographical issues, e.g., 'ref f' with an extra space in Sec. III.C and 'FCNq =20' in the Table II header; a careful proofread is needed.
  3. [Supplementary Sec. 3, Fig. 6] The caption states that σ7 and σ100 are computed from 200 repeated samplings, while the text says the standard deviation increases by a factor of 3.68; please clarify whether these are standard deviations of single-sample r or of subset means, and define the exact bootstrap procedure.
  4. [Abstract; Sec. I] The abstract and introduction claim this is 'the most extensive cross-platform quantum benchmarking effort to date'; please provide a citation or comparison with prior multi-device benchmarking studies (e.g., Refs. [29–32]) to substantiate this superlative.

Circularity Check

1 steps flagged · score 3.0 of 10

Empirical QPU measurements are independent; only the LR-QAOA parameter schedule is justified by the authors' prior work, giving a mild self-citation burden.

  1. self citation load bearing [Section II.A (LR-QAOA) and Supplementary Sec. 1, Table III]
    "We choose well-conditioned ramp schedules with observable signal growth in noise-free settings and balanced saturation under noise, validated in prior simulations [1]. ... These values were not tuned for performance on individual QPUs. Instead, they follow the observation from [1, Sec. III-B] that the optimal value of ∆γ,β decreases as Nq increases, in order to maintain algorithmic signal."

    The benchmark's central control parameter is the linear ramp slope ∆β,γ. Its values are not derived from first principles or from external benchmark data; they are taken from [1], the authors' own earlier LR-QAOA paper, and then assigned per backend and per size in Table III for FC experiments. Since the pass/fail metric reff depends on rmax (Eq. 8), and r(p) is sensitive to ∆ (Supp. Figs. 8a, 10b, 15), the cross-platform rankings are conditional on a schedule whose selection is justified by a self-citation. However, the measured r values on each QPU are new, independently obtained hardware data, so this is a load-bearing self-citation rather than an equivalence-by-construction of inputs and outputs.

full rationale

The core empirical content of the paper is not circular. The approximation ratios r are computed from measured bitstring samples (Eqs. 6-7) against optima obtained from CPLEX, and the random-sampler threshold is a classical statistical baseline (Supp. Sec. 3); no equation makes the QPU output equal to the input parameters by construction. The headline ranking, such as Quantinuum H2-1 passing the 56-qubit FC benchmark, is a direct experimental observation. The only identified circularity burden is the ramp-schedule choice: the paper states that schedules were 'validated in prior simulations [1]' and that per-size FC values follow 'the observation from [1, Sec. III-B]'. Reference [1] is the same group's prior LR-QAOA work, and the schedule affects which devices pass at which depths. This makes part of the protocol's validity rest on self-citation, but it does not reduce the measured hardware results to the prior paper's outputs. The per-backend ∆ values in Table III also raise a fairness concern relative to the Discussion's requirement that 'the same set of parameters must be used across all devices,' but that is an internal-consistency issue rather than a circular derivation. Overall, score 3: some self-citation is load-bearing, yet the central measurement content remains independent.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

No new physical entities are introduced. The free parameters are the ramp amplitude Delta_beta,gamma and the random-threshold convention, both of which directly influence which devices pass the benchmark. The axioms are standard domain assumptions about the benchmark metric, vendor data reliability, and routing decompositions.

free parameters (3)
  • Delta_beta,gamma for 1D-chain and NL benchmarks = 1
    Chosen from performance diagrams on ibm brisbane and ibm torino (Supp. Sec. 4 and 6) to maximize signal; applied across all 1D-chain/NL devices. A different fixed value could change pass/fail curves.
  • Delta_beta,gamma for FC benchmarks = 0.2 to 0.63 depending on backend and Nq (Table III)
    Set from the authors' prior observation [1] that the optimal Delta decreases as Nq increases; different backends use different values, so comparisons at a given Nq do not hold parameters fixed.
  • Random-sampler confidence threshold = 99.73% (3sigma over 100 random subsets)
    Defines pass/fail via Eq. (8); with N=7 samples the corresponding interval is wide (Fig. 6), so a 'pass' is a weaker claim than with 1000 samples.
assumptions (4)
  • domain assumption LR-QAOA with linear ramp parameters produces an approximation ratio that grows with depth in the absence of noise and saturates or decays under noise (Fig. 1(d)).
    This premise makes the approximation ratio a meaningful benchmark signal; it is validated in the authors' prior simulations [1], not independently in this paper.
  • domain assumption The 99.73% random-sampler interval is a valid statistical definition of meaningful algorithmic signal.
    Used in Eq. (8) and all pass/fail statements; the threshold is conventional rather than derived from the problem.
  • domain assumption Vendor-reported device parameters (gate errors, durations, layouts) are accurate at the time of the experiments.
    Table I and performance comparisons rely on vendor documentation; no independent calibration is performed.
  • standard math The swap network maps fully connected WMC problems to fixed-layout devices with the stated 3x gate overhead and preserves the algorithmic signal.
    Standard decomposition [42,43] used in Sec. 7 and in the gate-count formulas.

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Pith. "Pith review of Evaluating the performance of quantum processing units at large width and depth." pith.science (2026). https://pith.science/paper/BAZIRMYC

@misc{pith2026250206471,
  author       = {Pith},
  title        = {Pith review of: Evaluating the performance of quantum processing units at large width and depth},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/BAZIRMYC}},
  note         = {Machine review of arXiv:2502.06471}
}
read the original abstract

Quantum computers have now surpassed classical simulation limits, yet noise continues to limit their practical utility. As the field shifts from proof-of-principle demonstrations to early deployments, there is no standard method for meaningfully and scalably comparing heterogeneous quantum hardware. Existing benchmarks typically focus on gate-level fidelity or constant-depth circuits, offering limited insight into algorithmic performance at depth. Here we introduce a benchmarking protocol based on the linear ramp quantum approximate optimization algorithm (LR-QAOA), a fixed-parameter, deterministic variant of QAOA. LR-QAOA quantifies a QPU's ability to preserve a coherent signal as circuit depth increases, identifying when performance becomes statistically indistinguishable from random sampling. We apply this protocol to 24 quantum processors from six vendors, testing problems with up to 156 qubits and 10,000 layers across 1D-chains, native layouts, and fully connected topologies. This constitutes the most extensive cross-platform quantum benchmarking effort to date, with circuits reaching a million two-qubit gates. LR-QAOA offers a scalable, unified benchmark across platforms and architectures, making it a tool for tracking performance in quantum computing.

Figures

Figures reproduced from arXiv: 2502.06471 by the authors.

Figure 1
Figure 1. FIG. 1. Scheme for benchmarking quantum processing units (QPUs) using LR-QAOA. (a) Graph topologies used in the [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. FIG. 2. Approximation ratio versus number of LR-QAOA layers for 1D-chain WMC problems on IBM, IQM, Rigetti, and [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. FIG. 3. NL-based benchmarking using LR-QAOA for WMC problems on [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (12 more)
Figure 4
Figure 4. Figure 4: FIG. 4. Fully connected (FC) benchmarking using LR-QAOA for WMC problems with 5 to 56 qubits. (a) Approximation [PITH_FULL_IMAGE:figures/full_fig_p006_4.png]
Figure 5
Figure 5. Figure 5: FIG. 5. Comparison of LR-QAOA approximation ratios to random sampler baselines for fully connected WMC problems. [PITH_FULL_IMAGE:figures/full_fig_p012_5.png]
Figure 6
Figure 6. Figure 6: FIG. 6. Distribution of approximation ratios for 56-qubit FC WMC problems using 7 and 100 random samples. The standard [PITH_FULL_IMAGE:figures/full_fig_p013_6.png]
Figure 7
Figure 7. Figure 7: FIG. 7. Approximation ratios from LR-QAOA on [PITH_FULL_IMAGE:figures/full_fig_p013_7.png]
Figure 8
Figure 8. Figure 8: FIG. 8. 1D-chain WMC problems using LR-QAOA for [PITH_FULL_IMAGE:figures/full_fig_p014_8.png]
Figure 9
Figure 9. Figure 9: FIG. 9. (a) Correlation matrices [PITH_FULL_IMAGE:figures/full_fig_p015_9.png]
Figure 10
Figure 10. Figure 10: FIG. 10. Native layout benchmarking using LR-QAOA for WMC problems on [PITH_FULL_IMAGE:figures/full_fig_p016_10.png]
Figure 11
Figure 11. Figure 11: FIG. 11. Comparison of LR-QAOA results for 10 random 3- and 4-regular WMC instances on (a) 10-qubit and (b) 20-qubit [PITH_FULL_IMAGE:figures/full_fig_p017_11.png]
Figure 12
Figure 12. Figure 12: FIG. 12. (a) Linear SWAP network strategy. Colored circles represent logical qubits, and the vertical axis corresponds to [PITH_FULL_IMAGE:figures/full_fig_p017_12.png]
Figure 13
Figure 13. Figure 13: FIG. 13. Fully connected 20-qubit WMC problem solved using LR-QAOA with [PITH_FULL_IMAGE:figures/full_fig_p018_13.png]
Figure 14
Figure 14. Figure 14: FIG. 14. Projected execution time for fully connected LR-QAOA problems with [PITH_FULL_IMAGE:figures/full_fig_p018_14.png]
Figure 15
Figure 15. Figure 15: FIG. 15. Performance diagram for a 30-qubit 1D-chain WMC problem solved using LR-QAOA with [PITH_FULL_IMAGE:figures/full_fig_p019_15.png]

Discussion (0). Continue with ORCID to comment.

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Reviewed August 8, 2026 · model on record in the stance chip above.