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REVIEW 3 major objections 5 minor 46 references

Learning to decode logical circuits

T0 review · 3 major / 5 minor · reviewed 2026-08-16 · deepseek-v4-flash

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Pith's one-line read The paper claims that a modular recurrent decoder with one processing cell per logical gate can decode deep logical Clifford circuits with correlated errors from transversal CNOT gates, achieving accuracy competitive with exhaustive…

desk verdict Useful modular LSTM decoder for logical circuits, but the mirror-symmetric-only evaluation undercuts the general-circuit claims. read the letter →

arxiv 2504.16999 v1 pith:J67CYT4C submitted 2025-04-23 quant-ph

Yiqing Zhou , Chao Wan , Yichen Xu , Jin Peng Zhou , Kilian Q. Weinberger , Eun-Ah Kim This is my paper · ORCID
classification quant-ph
keywords quantumerrorcorrectionlogicalcircuitdecodingcorrelatederrorstransversalCNOTsurfacecoderecurrentneuralnetworkdecoderLSTMmirror-symmetricrandomCliffordcircuits
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Quantum error correction keeps a logical qubit alive, but decoding the syndrome data fast enough for real computation is a bottleneck, and entangling gates such as CNOT make it worse: a physical error on one qubit can propagate to another, producing correlated syndromes that standard matching decoders cannot handle directly. The paper argues that a single data-driven decoder, MCCD, can learn to handle these correlated patterns without being handed a noise model. MCCD is a modular recurrent network with one LSTM processing cell per logical gate and one hidden state per logical qubit; the CNOT cell ingests the hidden states and syndromes of both the control and target qubit, so error propagation is represented inside the network rather than in a hand-built graph. Trained on mirror-symmetric random Clifford circuits, where the forward and inverse circuits cancel so the correct answer is known, MCCD reports logical accuracy competitive with exhaustive most-likely-error decoding and with belief-propagation decoders, while its wall time grows roughly linearly with circuit depth for surface-code distances 3 and 5. If the claim holds, it removes a classical bottleneck for fault-tolerant logical circuits.

What carries the argument

The load-bearing object is a set of gate-specific LSTM processing cells, meaning long short-term memory recurrent units, connected through per-qubit hidden states, together with the mirror-symmetric random Clifford circuit used for training. A processing cell for a single-qubit gate updates one qubit's hidden state from the new syndrome; the two-qubit CNOT cell concatenates the hidden states and syndromes of control and target, updates both together, and splits the result back. Mirror-symmetric circuits supply ground-truth labels with no extra simulation cost, because a noiseless forward-then-inverse circuit returns the initial state; this lets the decoder be trained end to end with a cross-entropy loss while randomizing over circuits to avoid overfitting. The two-stage curriculum, which trains single-qubit modules first and then freezes them to train only the CNOT module, keeps training data cheap and focuses capacity on the correlated-error structure.

What would settle it

A concrete test: take the trained MCCD and run it on logical circuits that are not mirror-symmetric and whose physical noise is strongly biased, for example dominated by dephasing rather than the mixed Pauli channels simulated here, holding code distance and error rate fixed; if logical accuracy falls well below most-likely-error decoding or belief-propagation with ordered-statistics post-processing, or if wall time becomes superlinear with depth, the paper's generalization and scaling claims would be contradicted.

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Extended reading notes

Core claim

The central claim is that decoding a logical circuit can be recast as a supervised per-qubit classification problem and solved by a modular recurrent network whose structure mirrors the circuit's gate set. Each logical qubit carries a hidden state that tracks its error history, and each supported gate, including the entangling CNOT, has a dedicated processing cell that updates the involved qubits' states from the incoming syndrome. The CNOT cell receives the hidden states and syndromes of both control and target qubits at once, so it can represent the correlated errors that arise when a physical error on one qubit propagates through the gate to the other. The paper reports that MCCD, trained with a curriculum that first learns single-qubit gates and then adds the two-qubit cell, achieves logical accuracy competitive with most-likely-error decoding and belief-propagation with ordered-statistics post-processing on surface-code logical qubits of distance 3 and 5, while its wall time grows approximately linearly with circuit depth and remains far below the exhaustive methods.

Load-bearing premise

The accuracy and speed results transfer from the two mirror-symmetric random Clifford circuit templates and the single circuit-level noise model used in training to the logical circuits and hardware noise encountered in deployment.

Editorial extensions

If this is right

  • MCCD generalizes to logical circuits significantly deeper than any seen in training, with no observed degradation in logical accuracy for the tested depths.
  • Its wall time grows approximately linearly with circuit depth for code distances 3 and 5, making it markedly faster than exhaustive most-likely-error decoding and than belief-propagation with ordered-statistics post-processing at large depth for distance 5.
  • A single unified framework handles both single-qubit and entangling logical gates, including the CNOT-induced correlated errors that matching-based decoders cannot capture directly.
  • Because it learns from syndrome data rather than from a hand-built noise graph, MCCD is noise-model agnostic and only assumes the hardware's native logical gate set.
  • The modular design extends to new gate sets as hardware evolves, since each new logical operation gets its own processing cell.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Beyond the paper: if the linear wall-time scaling persists at larger code distances and with denser entangling layers, MCCD-type decoders could serve as real-time decoders inside the control loop of a fault-tolerant processor, not just as offline verification tools.
  • Beyond the paper: the mirror-symmetric training trick is not tied to Clifford gates; the same circuit-equals-its-inverse label scheme could generate training data for teleported non-Clifford gates, although the paper only tests transversal Clifford operations.
  • Beyond the paper: the noise-model-agnostic claim is only as broad as the single simulated neutral-atom-style noise model tested; a natural check is to retrain on a depolarizing or biased-noise model and compare transfer, a test the architecture invites but the paper does not perform.
  • Beyond the paper: the per-qubit LSTM hidden state has a fixed memory window, so very long-range temporal correlations in deep circuits may eventually be missed; extending the cells with attention or larger context would be a measurable test of that limit.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The manuscript introduces MCCD, a modular LSTM-based decoder for logical circuits built from transversal Clifford gates on surface-code logical qubits. The decoder maintains one hidden state per logical qubit, processes syndromes with gate-specific recurrent cells, and uses a two-qubit cell for CNOT-induced correlated errors. The authors train on mirror-symmetric random Clifford circuits (single-qubit Type I and CNOT-containing Type II) generated with Stim under a circuit-level noise model motivated by neutral-atom hardware, then test on unseen circuits of greater depth and at code distances d=3 and d=5. They benchmark logical accuracy and wall time against MWPM, MLE, and BP-OSD, reporting that MCCD achieves accuracy competitive with BP-OSD and superior speed scaling with circuit depth, especially for entangling circuits. The paper claims the framework is a noise-model-agnostic, general logical-circuit decoder.

Significance. If the central claims hold, the paper makes a useful contribution: a modular recurrent decoder that processes syndrome streams with per-gate cells is a natural architecture for logical circuits, and the ability to decode CNOT-induced correlated errors with roughly linear depth scaling would be practically valuable. The manuscript has real strengths: it provides open code, uses Stim for reproducible simulation, benchmarks against three established decoders, and demonstrates depth extrapolation beyond training depths. However, the empirical evidence is narrower than the abstract suggests: only mirror-symmetric circuits are tested, only one noise model is used, and the timing/accuracy figures lack statistical error bars. With additional tests and more careful claims, the work could be an important step toward practical circuit decoding; in its current form, the generality claims outrun the data.

major comments (3)
  1. [Main text, 'Mirror-symmetric random circuits' and Figs. 3-5] All training and test circuits are mirror-symmetric: a random unitary U followed by its reverse U†. This gives the syndrome stream a special temporal structure: errors created in the forward half are re-encountered in reverse order and conjugated by the backward gates, which an LSTM with memory can exploit. The only held-out variation is circuit depth (and d=3 vs d=5); non-mirror circuits, arbitrary gate sequences, and circuits with more than one CNOT per qubit per layer are never tested. The claim of a 'general circuit decoder' therefore is not established. I request experiments on non-mirror circuits (e.g., random Clifford circuits without enforcing U†, or deterministic logical algorithms such as Bell-state preparation followed by verification), plus circuits violating the one-CNOT-per-qubit-per-layer restriction, to show that the decoder generalizes beyond the mirrored training distribution.
  2. [Abstract and SM C.2] The abstract claims a 'noise-model agnostic solution,' but MCCD is trained and tested on trajectories generated from a single circuit-level noise model (SM C.2), and the conventional decoders are given that exact same noise model. No experiment varies the noise parameters or trains on one noise model and tests on another. As written, the noise-model-agnosticism claim is unsupported. Either add cross-noise-model transfer tests (e.g., train under the neutral-atom-inspired model and evaluate under depolarizing noise with different error rates, or at least under a perturbed noise channel) or substantially weaken the claim to 'does not require an explicit noise model at inference time.'
  3. [Figures 4 and 5] The central quantitative claims—logical accuracy and wall-time scaling—are presented without error bars, confidence intervals, or even the number of test trajectories used for each point. This matters because the differences between MCCD and BP-OSD accuracy appear small in some regimes, and the wall-time comparisons depend on implementation and hardware, which are not specified. Please report the sample size per data point, statistical uncertainty in the logical error rates, and the CPU/GPU hardware and software versions used for the timing measurements, and ideally run repeated timing measurements to estimate variability.
minor comments (5)
  1. [Abstract] The first sentence contains a grammatical error: 'an efficient polynomial-time decoding algorithms' should be 'efficient polynomial-time decoding algorithms.'
  2. [Main text, paragraph after Fig. 1] 'correlate errors' should be 'correlated errors' in the sentence 'We find MCCD to learn to decode correlate errors from a general circuit successfully.'
  3. [SM A, Eq. (A1)] The LSTM equations use h_i for the hidden state at time i, but the surrounding text refers to h_t and h_{t-1}; aligning notation would improve readability.
  4. [SM B, Table III] The table entry 'Training data size 500,000' combined with 'batch size 1024' does not immediately convey that this means 5×10^8 trajectory samples; the text clarifies this, but a footnote in the table would help.
  5. [Main text, 'Note' paragraph] The sentence 'Note - Toward the conclusion of this work, we noticed a recent work...' is awkward and sounds like an acknowledgment rather than a scientific note. It would be clearer as a normal reference comparison in the introduction or related-work section.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity found; the central claims rest on held-out simulation data and independent external baseline decoders.

full rationale

I examined the derivation chain from syndrome data to the claimed decoding capability. The training labels are generated by simulating mirror-symmetric random Clifford circuits and comparing final logical measurements with initial preparations; this is a direct construction of ground-truth logical flips, not an output of the decoder. The reported accuracies are measured on held-out test trajectories (deeper random circuits from the same two circuit families), and the conventional decoders (MLE, MWPM, BP-OSD) are independent external algorithms run on the same test trajectories. I found no equation in which a fitted parameter is renamed as a prediction, no load-bearing conclusion justified solely by a self-citation, and no ansatz imported through citation. The mirror-symmetric training distribution is a genuine limitation on the breadth of the 'general circuit' and 'noise-model agnostic' claims, but that is a question of external validity and distribution coverage, not circularity: the test results are not forced by construction. Hence score 0.

Assumptions & free parameters 2 free parameters · 5 assumptions · 0 invented entities

The central empirical claims rely on a trained neural network rather than a derivation from first principles. The ledger lists the fitted network weights and hyperparameters, the standard QEC formalism, the adopted noise model, and the architectural and training-distribution assumptions on which the reported performance depends. No new physical entities are introduced.

free parameters (2)
  • Trained LSTM and readout weights (single-qubit cells, two-qubit cell, main and auxiliary readouts) = Not stated; trained on 5e8 syndrome trajectories
    The decoder's outputs are produced entirely by these fitted weights; no closed-form decoder is supplied.
  • Network hyperparameters = Hidden sizes 64/128 (d=3) and 192/384 (d=5); 2 LSTM layers; ReLU; learning rate 0.001; auxiliary loss weight 0.5…
    Hand-chosen in SM Tables I-III; results may shift with these choices.
assumptions (5)
  • standard math Surface code stabilizer formalism and transversal Clifford logical gates provide a valid fault-tolerant encoding under circuit-level noise.
    Used throughout SM C.1 and the main text; not derived in this paper.
  • domain assumption The neutral-atom-motivated circuit-level noise model in SM C.2 matches the target hardware.
    All training and benchmarking data come from this model; no robustness to noise-model mismatch is demonstrated.
  • ad hoc to paper Mirror-symmetric random Clifford circuits of Type I and Type II are representative of the logical circuits MCCD must decode.
    Testing is restricted to these two templates; generalization to arbitrary circuit structure is assumed.
  • ad hoc to paper Per-qubit hidden states plus pair-wise two-qubit processing cells capture all relevant error correlations.
    Architecture choice in Fig. 2; multi-qubit correlations beyond pairwise interactions are neither modeled nor tested.
  • standard math A noiseless mirror circuit U U-dagger leaves the initial state unchanged, providing ground-truth labels.
    Used for cross-entropy training labels in the mirror-symmetric circuit scheme.

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Pith. "Pith review of Learning to decode logical circuits." pith.science (2026). https://pith.science/paper/J67CYT4C

@misc{pith2026250416999,
  author       = {Pith},
  title        = {Pith review of: Learning to decode logical circuits},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/J67CYT4C}},
  note         = {Machine review of arXiv:2504.16999}
}
read the original abstract

With the development of quantum hardware bringing the error-corrected quantum circuits to the near future, the lack of an efficient polynomial-time decoding algorithms for logical circuits presents a critical bottleneck. While quantum memory decoding has been well-studied, inevitable correlated errors introduced by entangling logical gates prevent the straightforward generalization of quantum memory decoders. We introduce a data-centric modular decoder framework, Multi-Core Circuit Decoder (MCCD), consisting of decoder modules corresponding to each logical operation supported by the quantum hardware. The MCCD handles both single-qubit and entangling gates within a unified framework. We train MCCD using mirror-symmetric random Clifford circuits, demonstrating its ability to effectively learn correlated decoding patterns. Through extensive testing on circuits significantly deeper than those used in training, we show that MCCD maintains high logical accuracy while exhibiting competitive polynomial decoding time across increasing circuit depths and code distances. When compared with conventional decoders like Minimum Weight Perfect Matching (MWPM), Most Likely Error (MLE), and Belief Propagation with Ordered Statistics Post-processing (BP-OSD), MCCD achieves competitive accuracy with substantially better time efficiency, particularly for circuits with entangling gates. Our approach represents a noise-model agnostic solution to the decoding challenge for deep logical quantum circuits.

Figures

Figures reproduced from arXiv: 2504.16999 by the authors.

Figure 2
Figure 2. FIG. 2. ML architecture. (a) For each element in the gate set, we train a separate decoder module. There is a one-to [PITH_FULL_IMAGE:figures/full_fig_p007_2.png] view at source ↗
Figure 3
Figure 3. FIG. 3. Mirror-symmetric random circuits. (a) A mirror symmetric circuit can be generated for an arbitrary circuit [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figure 4
Figure 4. FIG. 4. Decoding performance on Circuit Type I. (a)-(b) Logical accuracy versus circuit depth using surface code with code distance d = 3 and d = 5 for MCCD (red), MLE (yellow), BP-OSD (green), and MWPM (blue) decoders. (c)-(d) Wall time taken to decoding one syndrome trajectory with increasing circuit depth for a d = 3 and d = 5 surface code [PITH_FULL_IMAGE:figures/full_fig_p008_4.png] view at source ↗
Figures from the paper (1 more)
Figure 5
Figure 5. Figure 5: (a) (b) (c) (d) FIG. 5. Decoding performance on Circuit Type II. (a)-(b) Logical accuracy versus circuit depth using surface code with code distance d = 3 and d = 5 for MCCD (red), MLE (yellow) and BP-OSD (green) decoders. (c)-(d) Wall time taken to decoding one syndro…

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