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REVIEW 3 major objections 6 minor 2 cited by

Quantum Compiler Design for Qubit Mapping and Routing: A Cross-Architectural Survey of Superconducting, Trapped-Ion, and Neutral Atom Systems

T0 review · 3 major / 6 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read This survey argues that qubit mapping and gate scheduling is not one compiler problem but three, each shaped by the physics of a hardware platform, and it organizes existing solutions into one cross-architectural map.

desk verdict Useful cross-architectural survey, but the tables and the 'systematic' claim need work before it can be trusted as a map. read the letter →

arxiv 2505.16891 v2 pith:RZK6DTYD submitted 2025-05-22 quant-ph

Chenghong Zhu , Xian Wu , Zhaohui Yang , Jingbo Wang , Anbang Wu , Shenggen Zheng , Xin Wang This is my paper
classification quant-ph
keywords quantumcompilationqubitmappinggateschedulingsuperconductingqubitstrapped-ioncomputingneutralatomarrayshardware-awarecompilersNISQ
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This survey maps the qubit mapping and gate scheduling (M&S) problem across the three leading quantum hardware platforms: superconducting, trapped-ion, and neutral atom systems. Its core claim is that M&S is not a single compiler problem; each platform's physics dictates what routing means, from inserting SWAP gates on a fixed coupling graph, to shuttling ions between traps, to physically moving atoms in reconfigurable arrays. The paper categorizes superconducting compilers into solver-based, heuristic, and machine-learning families, traces trapped-ion compilers from linear-tape to QCCD to distributed architectures, and reviews neutral atom compilers for fixed, reconfigurable, and zoned arrays. It then identifies open directions: AI-driven compilation, application-specific compilers, fault-tolerant-era (FASQ) compilation, and standardized benchmarks. A reader would care because compilation overhead currently limits what noisy quantum hardware can execute.

What carries the argument

The organizing machinery is a two-axis hardware model: qubit connectivity, classified as local, reconfigurable, or all-to-all, and qubit parallelism, classified as low, moderate, or high. These two axes, together with the native gate set and noise model of each platform, define the constraint set that any M&S compiler must satisfy, and they are what make the three platforms complementary case studies. The paper also relies on the standard DAG representation of circuits and on per-platform cost models, such as the coupling graph for superconducting devices, the AOM zone and shuttle heating models for trapped ions, and the Rydberg blockade radius and movement-collision rules for neutral atoms. This machinery carries the argument by converting a scattered literature into a structured comparison, showing which methods generalize and which are platform-specific.

What would settle it

Run one standardized circuit suite through a superconducting, a trapped-ion, and a neutral atom compiler stack and compare the relative performance of solver-based, heuristic, and machine-learning methods; if the ranking reverses across platforms, the survey's categorization loses its predictive value. A simpler check: identify a mainstream architecture whose connectivity and parallelism lie outside the survey's three categories, which would refute the claim of full-spectrum coverage.

Watch

Extended reading notes

Core claim

The central discovery, stated on the survey's own terms, is that the hardware constraints of the three mainstream platforms span the full spectrum of compilation challenges, and that understanding them together reveals transferable methods and genuine gaps. Superconducting devices have fixed local connectivity, so the M&S problem is SWAP insertion on a static graph, and the field is mature enough to classify methods by whether they use exact solvers, heuristics, or machine learning. Trapped-ion devices have fully connected traps but dynamic topology through shuttling, so compilers must schedule ion movement, split, and merge operations; the survey traces this line from linear-tape devices to QCCD and distributed systems. Neutral atom devices add reconfigurable connectivity through atom movement and native multi-qubit gates with Rydberg blockade constraints, so routing is an atom-placement and movement problem rather than a SWAP-insertion problem. The survey concludes that compiler research for superconducting devices is relatively well developed, while trapped-ion and neutral atom compilers offer significant room for further exploration.

Load-bearing premise

The map is only as trustworthy as its sample: it assumes that superconducting, trapped-ion, and neutral atom systems cover the full span of compilation challenges, and that the unreviewed preprint compilers it cites correctly represent the state of the art.

Editorial extensions

If this is right

  • Compiler techniques that succeed on superconducting devices, including look-ahead heuristics and solver-based formulations, are already being adapted to trapped-ion and neutral atom platforms, and this cross-fertilization is likely to accelerate.
  • Exact solver-based methods are limited to small circuits, so scaling to large NISQ and fault-tolerant workloads will require heuristic and machine-learning approaches.
  • Neutral atom movement can outperform SWAP-based routing in both fidelity and circuit duration when the scheduler respects movement constraints and native multi-qubit gates.
  • Quantum error correction compilation is currently concentrated on superconducting devices, leaving trapped-ion and neutral atom QEC-aware compilers as an open area.
  • Standardized, platform-aware benchmarks are missing, so meaningful cross-platform comparison of compiler quality is not yet possible.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A fourth platform whose connectivity and parallelism fall outside the survey's three categories would test the completeness of the map; silicon spin qubits or photonic systems are candidates the survey does not analyze.
  • The survey's observation that initial mapping matters less as circuit depth grows could be turned into a quantitative scaling law, connecting circuit size to the value of initial placement versus routing.
  • Machine-learning compilers may eventually serve as a unified layer across platforms, but the open correctness problem means hybrid systems that pair learned policies with formal verification are the more likely near-term outcome.
  • A standardized benchmark suite parameterized by platform constraints would let the community answer the survey's implicit question, which compiler family wins under a given hardware profile.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. This survey reviews qubit mapping and gate scheduling (M&S) research for three quantum hardware platforms: superconducting, trapped-ion, and neutral atom systems. It categorizes superconducting compilers into solver-based, heuristic-based, and machine-learning-based approaches; organizes trapped-ion compilation by architecture evolution from linear-tape devices to QCCD and distributed systems; and surveys neutral-atom compilation for fixed arrays, reconfigurable arrays, and zoned architectures. The paper also discusses application-specific compilers, QEC-oriented compilation, and several future research directions, including AI-driven compilation, standardized benchmarks, and platform-aware fault-tolerant compilers.

Significance. If the survey's categorization is accurate, it would be a useful cross-architectural reference for quantum compiler researchers, particularly for the less mature trapped-ion and neutral-atom areas. The paper's strengths include its broad coverage of recent work, explicit statements of hardware constraints for each platform, and the inclusion of trapped-ion noise models and neutral-atom movement rules. However, because the paper's central contribution is an organized map of the literature, its value depends on the reliability of its tables and the representativeness of the selected corpus; the integrity issues identified below currently undermine that central claim and need to be addressed.

major comments (3)
  1. [§5.1, Table 5] Table 5 lists the same reference [177] twice, once with architecture 'RAA' and once with 'Zoned Architecture,' while compilers discussed in §5.3 and §5.4 (Q-Pilot [191], Enola [178], NALAC [171], and ZAP [72]) have no table rows. Since the survey's contribution is an organized categorization of 'major' algorithms and Table 5 is the reader's index to the neutral-atom literature, these entries must be deduplicated and completed before the coverage claim can be considered reliable.
  2. [Table 4] The row for [148] lists 'Circuit Synthesis' as the problem and 'Reinforcement Learning' as the algorithm in a table of trapped-ion M&S compilers, but the paper's declared scope in §2.2 is qubit mapping and gate scheduling, and [148] is not discussed in the trapped-ion compiler sections. Including a circuit-synthesis paper in an M&S summary table is a misassignment that undermines the table's fidelity as an index.
  3. [§1, Contributions] The abstract and the contribution list describe the review as 'systematic,' but no search protocol, inclusion/exclusion criteria, time window, or quality filter is provided. This omission is not merely procedural: combined with the table-level integrity errors noted above, the reader cannot verify that the surveyed corpus is representative of the 'major' algorithms the paper claims to organize. The authors should either state their selection methodology or qualify the coverage claim.
minor comments (6)
  1. [§4.3, Eq. (4)] The QCCD fidelity model in Eq. (4) is presented without a citation or derivation; the variables A and ¯n are described in prose, but the source of the formula should be given, since the survey later uses such models for qualitative comparisons.
  2. [§5.4] The heading 'Zoned Architecture Neural Atom Devices' and the phrase 'neural atom compiler design' in §5.1 use 'neural' where 'neutral' is intended.
  3. [§2.1] The text contains the typo 'trapped-ion devics' for 'trapped-ion devices.'
  4. [§1] The sentence 'it is necessary to perform and effective conversion process' should read 'an effective conversion process.'
  5. [References] Reference [81] lists the journal as 'A VS Quantum Science'; the correct name is 'AVS Quantum Science.'
  6. [§4.3] The paragraph beginning 'Murali et al. [124] first introduce a compiler' is immediately followed by another sentence beginning 'Murali et al. [124] also examine'; these should be merged to avoid the appearance of two distinct works.

Circularity Check

0 steps flagged · score 2.0 of 10

No load-bearing circularity; the survey's categorization is independent, with only minor non-load-bearing self-citations.

full rationale

This is a survey rather than a derivation pipeline, so the main circularity patterns do not apply. The only equations in the paper are noise models quoted from prior work (Eqs. 2-4); none is fitted here and none is used to generate a new prediction. The central organizational claim, that qubit-mapping research is best categorized by the hardware platforms of superconducting, trapped-ion, and neutral atom systems, is supported by the external literature the survey catalogs. The authors do cite several of their own works (e.g., BOSS [201], S-SYNC [218], Phoenix [208], ZAP [72], and benchmark paper [220]), but these appear as surveyed examples and not as authority for the survey's structure, and no self-citation is invoked as a uniqueness theorem or as the sole justification for a classification. The cited formula F_shuttle = 1 - epsilon_shuttle * m is a definitional linear-loss model from [201], not a derived result claimed by this paper. The internal table inconsistencies (e.g., reference [177] appearing twice in Table 5, with NALAC [171] and ZAP [72] discussed in Section 5.4 but absent from the table) and the absence of a formal search protocol are survey-reliability concerns, but they are not circularity. The score of 2 reflects only the presence of minor, non-load-bearing self-citations.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The survey rests on domain assumptions about which hardware platforms are mainstream and which compilation tasks are central. It also imports standard mathematical results and prior noise models without re-deriving them.

assumptions (4)
  • domain assumption Qubit mapping and gate scheduling is the key step in quantum compilation.
    The entire survey is framed around M&S as the focus of quantum compilers, stated in Section 2.2 and the contributions.
  • domain assumption The three platforms (superconducting, trapped-ion, neutral atom) comprehensively cover the key compilation challenges of connectivity, parallelism, and qubit modality.
    Stated in Section 2.3: 'these three hardware platforms not only because they represent the most rapidly advancing and promising candidates... but also because their distinct physical characteristics comprehensively cover the key compilation challenges.'
  • standard math The NP-hardness results for qubit mapping and SWAP minimization are correct.
    The paper cites Siraichi et al. [167] for NP-completeness and Botea et al. [23] for NP-hardness in Section 3.1, and relies on these to justify solver-based approaches.
  • domain assumption The trapped-ion noise models in Eqs. (2)-(4) accurately describe fidelity degradation.
    Section 4.2 and 4.3 use these models from prior work (Wu et al. [202], Murali et al. [124]) to compare compiler performance, without independent validation in this paper.

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Cite this review

Pith. "Pith review of Quantum Compiler Design for Qubit Mapping and Routing: A Cross-Architectural Survey of Superconducting, Trapped-Ion, and Neutral Atom Systems." pith.science (2026). https://pith.science/paper/RZK6DTYD

@misc{pith2026250516891,
  author       = {Pith},
  title        = {Pith review of: Quantum Compiler Design for Qubit Mapping and Routing: A Cross-Architectural Survey of Superconducting, Trapped-Ion, and Neutral Atom Systems},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/RZK6DTYD}},
  note         = {Machine review of arXiv:2505.16891}
}
read the original abstract

Quantum hardware development is progressing rapidly with substantial advancements achieved across leading platforms, including superconducting circuits, trapped-ion systems, and neutral atom arrays. As the pursuit of practical quantum advantage continues, efficient quantum program compilation becomes essential for transforming high-level representations of quantum algorithms into physically executable circuits. A fundamental challenge in this process is qubit mapping and gate scheduling, which play a critical role in adapting compiled circuits to the architectural constraints and physical limitations of specific quantum hardware. In this survey, we systematically review and categorize research on the qubit mapping and routing problems across the three mainstream quantum hardware platforms. We primarily explore the development of hardware-aware compilers for superconducting platforms, classifying existing methods into solver-based, heuristic-based, and machine learning-based approaches, and analyze their optimization targets, including gate count, circuit duration, fidelity, and scalability. Furthermore, we examine the evolution of trapped-ion and neutral atom devices, analyzing the distinct challenges posed by their hardware characteristics and highlighting specialized compilers tailored to these unique physical constraints. Finally, we summarize the key challenges and identify some promising opportunities for future research in quantum compiler design across these hardware platforms.

Figures

Figures reproduced from arXiv: 2505.16891 by the authors.

Figure 1
Figure 1. Overview of the three mainstream quantum hardware architectures and their graph illustrations: (a) [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. An illustration of a circuit’s DAG representation. The front layer of the graph is made up of the nodes [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. The workflow of quantum program compilation. [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (6 more)
Figure 4
Figure 4. Figure 4: Common structures of superconductivity devices and their corresponding connectivity graphs. [PITH_FULL_IMAGE:figures/full_fig_p008_4.png]
Figure 5
Figure 5. Figure 5: An illustration of linear-tape trapped-ion chips demonstrates that qubits within the Acousto-Optic [PITH_FULL_IMAGE:figures/full_fig_p018_5.png]
Figure 6
Figure 6. Figure 6: A modular Quantum Charge Coupled Device (QCCD) consists of several traps, each of which is initial [PITH_FULL_IMAGE:figures/full_fig_p021_6.png]
Figure 7
Figure 7. Figure 7: Shuttling in a QCCD system which has linear device topology. Extra split and merge operations are [PITH_FULL_IMAGE:figures/full_fig_p021_7.png]
Figure 8
Figure 8. Figure 8: RAA with fixed and movable atoms. It is important to note that while the AOD atom array is movable, [PITH_FULL_IMAGE:figures/full_fig_p028_8.png]
Figure 9
Figure 9. Figure 9: The typical zoned architecture, proposed by Decker [PITH_FULL_IMAGE:figures/full_fig_p030_9.png]

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Forward citations

Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Protected quantum gates using qubit doublons in dynamical optical lattices

    quant-ph 2025-07 conditional novelty 7.0 of 10

    Qubit doublons in a dynamical optical lattice enable a purely geometric SWAP gate for fermionic atoms, demonstrated at 99.91(7)% loss-corrected fidelity.

  2. M\"obius-Guided Diagonal-Gate Compilation with Native Multiqubit Controlled-Phase Gates on Neutral-Atom Processors

    quant-ph 2026-07 conditional novelty 6.0 of 10

    Möbius inversion turns diagonal phase layers into phase hypergraphs that a neutral-atom scheduler can execute as native multiqubit controlled-phase gates when routing and error costs favor them.

Reference graph

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Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.