Paper Citation Record · LEDGER

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization

As of 11 August 2026, this Paper Citation Record lists 32 of 32 outbound references and 0 inbound Pith citation observations for arXiv:2507.17962.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2507.17962 v1

Coverage vector

measured 32 of 32 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-06T14:42:04.951683Z

measured 32 of 32 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-10T06:31:04.303077+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

32 of 32 outbound references displayed

verified exact0
verified fuzzy29
unresolved3
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 13b4f0d3-5f6e-4474-8d13-39441a5e89b2 · outbound

This paper cites Improving classification accuracy of a machine learning approach for FPGA timing closure.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Improving classification accuracy of a machine learning approach for FPGA timing closure

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.186275Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 988bade3-ff3d-444a-8a34-31f5aec03d31 · outbound

This paper cites Conget al.,”FPGA HLS today: successes, challenges, and opportu- nities”,ACM TRETS, vol.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Conget al.,”FPGA HLS today: successes, challenges, and opportu- nities”,ACM TRETS, vol

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.178962Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 4b70a47e-3b39-47c1-a2cd-a9c90d6e6ac9 · outbound

This paper cites Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.172124Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation fa800604-d987-4358-aa77-f16081d3c9dc · outbound

This paper cites LAMDA: Learning-assisted multi-stage autotuning for FPGA design closure.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization LAMDA: Learning-assisted multi-stage autotuning for FPGA design closure

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.164512Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation beebcd8e-9383-4edf-b6c2-2d837330a907 · outbound

This paper cites Correlated multi-objective multi-fidelity optimization for HLS directives design.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Correlated multi-objective multi-fidelity optimization for HLS directives design

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.157832Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 1b183deb-0435-4144-80f4-fd64b4bb1905 · outbound

This paper cites AMD Vitis HLS, High-Level Synthesis Tool,.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization AMD Vitis HLS, High-Level Synthesis Tool,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.151113Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 4e13d935-de9c-40e4-96fd-d78424fdb1f8 · outbound

This paper cites HLSPilot: LLM-based high-level synthesis.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization HLSPilot: LLM-based high-level synthesis

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.144350Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 22a5bc49-ab37-490d-98e5-cca56b895355 · outbound

This paper cites Automatic hardware pragma insertion in high-level synthesis: A non-linear programming approach.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Automatic hardware pragma insertion in high-level synthesis: A non-linear programming approach

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.137698Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 6f37f00e-fe3d-4445-be70-5ce134804085 · outbound

This paper cites Democratizing domain-specific computing.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Democratizing domain-specific computing

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.130646Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation bdab5f52-44f5-4a5f-8f31-4a882047f564 · outbound

This paper cites Lahtiet al.,”High-level Synthesis for FPGAs—A Hardware Engi- neer’s Perspective”,IEEE Access, 2025.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Lahtiet al.,”High-level Synthesis for FPGAs—A Hardware Engi- neer’s Perspective”,IEEE Access, 2025

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.123709Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation a7b69a77-c4e2-4786-a478-9d914f7ee790 · outbound

This paper cites [Online].

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization [Online]

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.116815Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 5987409e-4045-484b-991b-59e56b2375c2 · outbound

This paper cites Accelerating FPGA prototyping through predictive model- based HLS design space exploration.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Accelerating FPGA prototyping through predictive model- based HLS design space exploration

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.110091Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation f250a283-35f8-4609-9b04-fbe1a0fdd371 · outbound

This paper cites Lattice-Traversing Design Space Exploration for High Level Synthesis.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Lattice-Traversing Design Space Exploration for High Level Synthesis

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.103439Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 183b3efe-33cd-4e98-9136-860992074fec · outbound

This paper cites AutoDSE: Enabling software programmers to design efficient FPGA accelerators.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization AutoDSE: Enabling software programmers to design efficient FPGA accelerators

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.096675Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation dd1fa933-bf8b-4cd6-a5a2-b300730a1c0d · outbound

This paper cites Robust GNN-based representation learning for HLS.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Robust GNN-based representation learning for HLS

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.089993Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 51290fc8-cdb7-4bb9-b7ef-61160c1b1642 · outbound

This paper cites LIFT: LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuning.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization LIFT: LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuning

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-06T14:42:04.912192Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 1f713449-5256-4ed1-ac52-6ccf050493e1 · outbound

This paper cites Sherlock: A multi-objective design space exploration framework.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Sherlock: A multi-objective design space exploration framework

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.083360Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 50095509-5148-45d7-891e-aa97638f8825 · outbound

This paper cites Check Your Facts and Try Again: Improving Large Language Models with External Knowledge and Automated Feedback.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Check Your Facts and Try Again: Improving Large Language Models with External Knowledge and Automated Feedback

Reference 18

Resolution: unresolved; no resolver link, observed 2026-08-06T14:42:04.917259Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 64b834d1-1050-4fcd-82d7-706b8b172000 · outbound

This paper cites Opentuner: An extensible framework for program autotuning.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Opentuner: An extensible framework for program autotuning

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.076747Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation bad6127c-a34f-4f1a-b351-6f5dbb874862 · outbound

This paper cites Efficient task transfer for HLS DSE.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Efficient task transfer for HLS DSE

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.069894Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 4866aeb6-d52e-4290-a347-ef9e6fbb0269 · outbound

This paper cites Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.063549Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 8243b095-0266-47b9-812a-cfc7a8bbe40d · outbound

This paper cites Lin-analyzer: A high-level performance analysis tool for FPGA-based accelerators.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Lin-analyzer: A high-level performance analysis tool for FPGA-based accelerators

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.056574Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 74d92f0f-6e75-4cf8-9b9e-35650bf9c8b5 · outbound

This paper cites COMBA: A comprehensive model-based analysis frame- work for high level synthesis of real applications.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization COMBA: A comprehensive model-based analysis frame- work for high level synthesis of real applications

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.049507Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation b89ce709-3d48-4c76-a497-9805440d886d · outbound

This paper cites ScaleHLS: A new scalable high-level synthesis framework on multi-level intermediate representation.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization ScaleHLS: A new scalable high-level synthesis framework on multi-level intermediate representation

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.042466Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 847f7843-837f-4def-85ac-f1434490ea48 · outbound

This paper cites Autoannotate: Reinforcement learning based code annotation for high level synthesis.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Autoannotate: Reinforcement learning based code annotation for high level synthesis

Reference 25

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.035611Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 71544353-d8d1-4fe8-86d0-0d3f112bde4f · outbound

This paper cites AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization AutoHLS: Learning to Accelerate Design Space Exploration for HLS Designs

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.028469Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation e28044b9-f748-4428-a8dc-3cae27ea80a1 · outbound

This paper cites Evolutionary large language models for hardware security: A comparative survey.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization Evolutionary large language models for hardware security: A comparative survey

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.021009Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation a859fee3-dc5d-4a64-8e46-770077dc8db4 · outbound

This paper cites LLM-IFT: LLM-Powered Information Flow Track- ing for Secure Hardware.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization LLM-IFT: LLM-Powered Information Flow Track- ing for Secure Hardware

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.013284Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 8b659837-5d7c-425a-b77b-784d77b459ee · outbound

This paper cites RTL++: Graph-enhanced LLM for RTL Code Generation.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization RTL++: Graph-enhanced LLM for RTL Code Generation

Reference 29

Resolution: unresolved; no resolver link, observed 2026-08-06T14:42:04.944107Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 515e2bc9-ace4-4dbb-addd-273597ece071 · outbound

This paper cites CHStone: A benchmark program suite for practical C-based high-level synthesis.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization CHStone: A benchmark program suite for practical C-based high-level synthesis

Reference 30

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:05.005917Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation 2025a4a7-61ff-46e1-aef6-9aeab1fe5e72 · outbound

This paper cites LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:04.998695Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Observation e3621c51-aa93-4149-99b8-f9b7039dcc27 · outbound

This paper cites MachSuite: Benchmarks for accelerator design and customized architectures.

TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization MachSuite: Benchmarks for accelerator design and customized architectures

Reference 32

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:42:04.990896Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

Pith citing papers

No inbound Pith citation observations are available.