Paper Citation Record · LEDGER

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators

As of 18 August 2026, this Paper Citation Record lists 48 of 48 outbound references and 1 inbound Pith citation observation for arXiv:2507.20420.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2507.20420 v1

Coverage vector

measured 48 of 48 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-15T17:48:51.873107Z

measured 49 of 49 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-18T06:34:40.430872+00:00

measured 1 of 1 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-05T10:41:48.148368Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: pith, observed 2026-08-05T10:41:48.241310Z

Reference resolution

48 of 48 outbound references displayed

verified exact4
verified fuzzy6
unresolved35
parse uncertain0
malformed identifier2
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External citation measurements

No source-named external measurement is stored.

Outbound references

Observation ea3b0abe-b37c-47c8-b528-fc2120f2fb34 · outbound

This paper cites ImageNet classification with deep convolutional neural networks,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators ImageNet classification with deep convolutional neural networks,

Reference 1

Resolution: unresolved; no resolver link, observed 2026-08-15T17:48:51.016592Z

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Observation 64521a3e-7779-4b9c-8862-d95c4eb05319 · outbound

This paper cites Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks,

Reference 2

Resolution: unresolved; no resolver link, observed 2026-08-15T17:48:51.021959Z

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Observation 9efef614-7e81-4cdc-befa-cc116d267762 · outbound

This paper cites ConvFusion: A Model for Layer Fusion in Convolutional Neural Networks,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators ConvFusion: A Model for Layer Fusion in Convolutional Neural Networks,

Reference 3

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Unavailable: canonical work link unavailable.

Observation 27fd1bf4-4546-43f9-869f-a51d0dc35fa1 · outbound

This paper cites Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA,

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-15T17:48:51.031316Z

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Observation cbbe9d32-d8b5-44c0-a19c-04fa120758f7 · outbound

This paper cites Characterizing and Demystifying the Implicit Convolution Algorithm on Commercial Matrix- Multiplication Accelerators,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Characterizing and Demystifying the Implicit Convolution Algorithm on Commercial Matrix- Multiplication Accelerators,

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-15T17:48:51.036017Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f506852c-b565-4c37-8ee7-55d36f502579 · outbound

This paper cites CNNFlow: Memory -driven Data Flow Optimization for Convolutional Neural Networks,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators CNNFlow: Memory -driven Data Flow Optimization for Convolutional Neural Networks,

Reference 6

Resolution: verified exact; doi, observed 2026-08-15T17:48:52.335014Z

Source-reported events for the cited work

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Observation 61f6f28d-672c-4049-8d35-dc5d6bc5ac14 · outbound

This paper cites Energy-Efficient Dataflow Scheduling of CNN Applications for Vector-SIMD DSP,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Energy-Efficient Dataflow Scheduling of CNN Applications for Vector-SIMD DSP,

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-15T17:48:51.045852Z

Source-reported events for the cited work

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Observation 50483885-2792-40ba-a42b-550a93f7c0c3 · outbound

This paper cites parallel for.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators parallel for

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T17:48:54.615923Z

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Observation 751c193f-21cd-42c5-9384-b3b707ae9ced · outbound

This paper cites A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective,

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-15T17:48:51.056180Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a4770345-3891-4002-bba4-468b03ca8e97 · outbound

This paper cites FPGA-based Acceleration for Convolutional Neural Networks: A Comprehensive Review.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators FPGA-based Acceleration for Convolutional Neural Networks: A Comprehensive Review

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-15T17:48:51.050585Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4d171b05-3c56-44a4-91ce-2af0363ae466 · outbound

This paper cites Going Deeper with Embedded FPGA Platform for Convolutional Neural Network,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Going Deeper with Embedded FPGA Platform for Convolutional Neural Network,

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-15T17:48:51.064991Z

Source-reported events for the cited work

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Observation ae43a257-1744-4986-8045-592be5dbada2 · outbound

This paper cites fpgaConvNet: Mapping Regular and Irregular Convolutional Neural Networks on FPGAs,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators fpgaConvNet: Mapping Regular and Irregular Convolutional Neural Networks on FPGAs,

Reference 12

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Source-reported events for the cited work

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Observation 1b8a3ff3-2d0b-4017-9b6b-026497524b0b · outbound

This paper cites Spatiotemporal Strategies for Long -Term FPGA Resource Management,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Spatiotemporal Strategies for Long -Term FPGA Resource Management,

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-15T17:48:51.074235Z

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Observation 95d7651b-942e-4d2a-8483-cc2f4852a086 · outbound

This paper cites Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks,

Reference 14

Resolution: unresolved; no resolver link, observed 2026-08-15T17:48:51.069641Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 913bc887-9acf-4c42-9a34-3a5e6e393827 · outbound

This paper cites Messaging-based Intelligent Processing Unit (m -IPU) for next generation AI computing.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Messaging-based Intelligent Processing Unit (m -IPU) for next generation AI computing

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T17:48:54.582279Z

Source-reported events for the cited work

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Observation 7614a240-c6d9-499e-b429-7cc3cd848c5a · outbound

This paper cites Accelerating PageRank Algorithmic Tasks with a new Programmable Hardware Architecture,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Accelerating PageRank Algorithmic Tasks with a new Programmable Hardware Architecture,

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-15T17:48:51.133827Z

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Unavailable: canonical work link unavailable.

Observation 53358b9f-cbe9-4d7e-b22b-044d7849cd3c · outbound

This paper cites DeLTA: GPU Performance Model for Deep Learning Applications with In -Depth Memory System Traffic Analysis,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators DeLTA: GPU Performance Model for Deep Learning Applications with In -Depth Memory System Traffic Analysis,

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-15T17:48:51.368412Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 5a9393c3-5593-46dc-b0e3-0801875bc81b · outbound

This paper cites Implications of memory embedding and hierarchy on the performance of MAVeC AI accelerators,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Implications of memory embedding and hierarchy on the performance of MAVeC AI accelerators,

Reference 18

Resolution: unresolved; no resolver link, observed 2026-08-15T17:48:51.282819Z

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Observation ed45d1ed-d695-4ad0-8b93-f3a74a05bf69 · outbound

This paper cites Fast Training of Convolutional Networks through FFTs.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Fast Training of Convolutional Networks through FFTs

Reference 19

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Observation 77687664-63f5-4f4b-9868-5a70825c4232 · outbound

This paper cites High-Performance Winograd Based Accelerator Architecture for Convolutional Neural Network,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators High-Performance Winograd Based Accelerator Architecture for Convolutional Neural Network,

Reference 20

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Observation 165774c5-b225-4766-9106-098918b83de1 · outbound

This paper cites White paper Lower Numerical Precision Deep Learning Inference and Training,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators White paper Lower Numerical Precision Deep Learning Inference and Training,

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T17:48:54.566618Z

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Observation ee2ff2e8-35e2-4500-9463-7d75dd0b2256 · outbound

This paper cites cuDNN: Efficient Primitives for Deep Learning.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators cuDNN: Efficient Primitives for Deep Learning

Reference 22

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Observation 31829e4a-c225-4460-9d5e-aaaf953a7550 · outbound

This paper cites Accelerating Deep Convolutional Neural Networks Using Number Theoretic Transform,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Accelerating Deep Convolutional Neural Networks Using Number Theoretic Transform,

Reference 24

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Observation 7ce06b05-3591-43bb-b1f8-9a72ae66973c · outbound

This paper cites An Energy -Efficient GeMM -Based Convolution Accelerator With On -the-Fly im2col,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators An Energy -Efficient GeMM -Based Convolution Accelerator With On -the-Fly im2col,

Reference 25

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Observation 81f83d14-b54e-4eea-956d-82071a6595f5 · outbound

This paper cites Design and Implementation of an NoC-Based Convolution Architecture With GEMM and Systolic Arrays,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Design and Implementation of an NoC-Based Convolution Architecture With GEMM and Systolic Arrays,

Reference 26

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Observation 96c85c6b-fc77-4d71-9a93-a199ad46397e · outbound

This paper cites Coarse -Grained Reconfigurable Array (CGRA),.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Coarse -Grained Reconfigurable Array (CGRA),

Reference 27

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Observation 7ab40867-e40c-418e-8e17-0e46f23b7b4e · outbound

This paper cites Can FPGAs Beat GPUs in Accelerating Next -Generation Deep Neural Networks?,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Can FPGAs Beat GPUs in Accelerating Next -Generation Deep Neural Networks?,

Reference 28

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Observation 2d5d73ad-589c-46cd-910e-92c52536556d · outbound

This paper cites an unresolved cited work.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Unresolved cited work

Reference 29

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Observation abb2f081-d7b6-4fbe-8277-a55be7eb5fd4 · outbound

This paper cites dMazeRunner: Optimizing Convolutions on Dataflow Accelerators,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators dMazeRunner: Optimizing Convolutions on Dataflow Accelerators,

Reference 30

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Observation 90e31ae1-e6e7-400d-a60f-1428b0c965f9 · outbound

This paper cites Twenty Years of Automated Methods for Mapping Applications on CGRA,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Twenty Years of Automated Methods for Mapping Applications on CGRA,

Reference 31

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Observation cb4c74e5-37c4-47ad-a51c-235db6d3c439 · outbound

This paper cites Eyeriss: An Energy -Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Eyeriss: An Energy -Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks,

Reference 32

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Observation 5d1c7c7c-5f76-4e4f-9d54-2b59c21759ad · outbound

This paper cites TVM: An Automated End-to-End Optimizing Compiler for Deep Learning.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators TVM: An Automated End-to-End Optimizing Compiler for Deep Learning

Reference 33

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Observation 7a5bd116-68f2-4440-afb7-ac22d42b41f1 · outbound

This paper cites Timeloop: A Systematic Approach to DNN Accelerator Evaluation,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Timeloop: A Systematic Approach to DNN Accelerator Evaluation,

Reference 34

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Observation 57dfa75b-8069-44b0-8506-9e0e23e2fe1e · outbound

This paper cites Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs,

Reference 35

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Observation ab390b9e-7306-466a-87e7-78b6b0f09480 · outbound

This paper cites Occam: Optimal Data Reuse for Convolutional Neural Networks,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Occam: Optimal Data Reuse for Convolutional Neural Networks,

Reference 36

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Observation 8b244257-3c95-4c23-afa8-c1489dc93f5d · outbound

This paper cites TIRAMISU: A Polyhedral Compiler for Expressing Fast and Portable Code.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators TIRAMISU: A Polyhedral Compiler for Expressing Fast and Portable Code

Reference 37

Resolution: verified exact; doi, observed 2026-08-15T17:48:52.307024Z

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Observation 00dfa447-af6f-451b-87de-c50983bdd679 · outbound

This paper cites Ragan -Kelley, C.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Ragan -Kelley, C

Reference 38

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Observation 193e1507-9154-479f-a31a-b57eec30b64d · outbound

This paper cites On -Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators On -Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators,

Reference 39

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Observation 455fca75-f5d6-491a-8598-43e9dac6b4fe · outbound

This paper cites Parashar et al., “SCNN,” in Proceedings of the 44th Annual International Symposium on Computer Architecture, New York, NY, USA: ACM, Jun.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Parashar et al., “SCNN,” in Proceedings of the 44th Annual International Symposium on Computer Architecture, New York, NY, USA: ACM, Jun

Reference 40

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Observation b32b9840-a485-486a-a953-cb0b1688893c · outbound

This paper cites Sze, Y.-H.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Sze, Y.-H

Reference 41

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Source-reported events for the cited work

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This paper cites Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead,

Reference 42

Resolution: unresolved; no resolver link, observed 2026-08-15T17:48:51.852005Z

Source-reported events for the cited work

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Observation b91f556e-f7c0-4498-af8f-c14f25f27f9e · outbound

This paper cites an unresolved cited work.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Unresolved cited work

Reference 43

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Source-reported events for the cited work

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Observation a1bb2fd2-2f17-4662-a19e-36c32301a05a · outbound

This paper cites FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural Networks,

Reference 44

Resolution: verified exact; doi, observed 2026-08-15T17:48:52.095486Z

Source-reported events for the cited work

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Observation 6d51623c-dd1a-43aa-baf6-da32fa122fa2 · outbound

This paper cites Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow,

Reference 45

Resolution: unresolved; no resolver link, observed 2026-08-15T17:48:51.873107Z

Source-reported events for the cited work

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Observation 3efbc610-6c40-40eb-a7bd-1ae7e2711233 · outbound

This paper cites Krishna, H.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Krishna, H

Reference 46

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T17:48:54.534434Z

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Observation 14441717-b98e-46e3-85dd-8c8ff1e703cb · outbound

This paper cites Here, each depth slice (i.e.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Here, each depth slice (i.e

Reference 48

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Observation d313950e-fca4-4f7e-b9e3-40c6dc59966d · outbound

This paper cites dMazeRunner,.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators dMazeRunner,

Reference 49

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Observation 0823ede6-9ad8-46c6-ab11-742dd77a8413 · outbound

This paper cites an unresolved cited work.

Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators Unresolved cited work

Reference 2020

Resolution: verified exact; doi, observed 2026-08-15T17:48:51.930538Z

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Pith citing papers

Observation 2b268739-5596-4af4-bd79-55dfedc6b3a4 · inbound

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs cites this paper.

Hardware-Aware Data and Instruction Mapping for AI Tasks: Balancing Parallelism, I/O and Memory Tradeoffs Demystifying the 7-D Convolution Loop Nest for Data and Instruction Streaming in Reconfigurable AI Accelerators

Reference 42

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Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.