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REVIEW 4 major objections 5 minor 41 references

Optimizing Tensor Network Partitioning using Simulated Annealing

T0 review · 4 major / 5 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read A simulated-annealing refinement of tensor-network partitioning finds cheaper contraction paths than generic hypergraph partitioning in most tested quantum circuits.

desk verdict Useful SA-based partition refinement with a flawed head-to-head benchmark: the Cotengra baseline is scored on total flops while the new method is scored on critical-path time. read the letter →

arxiv 2507.20667 v1 pith:ZFMWR4NJ submitted 2025-07-28 quant-ph

Manuel Geiger , Qunsheng Huang , Christian B. Mendl This is my paper
classification quant-ph MSC 81P6868W1568R1065K10
keywords tensornetworkssimulatedannealingdistributedmemorygraphpartitioningquantumcircuitsimulationcontractiontreetime-to-solutionhigh-performancecomputing
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper argues that splitting a tensor network across distributed-memory nodes should be optimized with the actual cost of the contraction in mind, not with generic hypergraph cuts alone. It introduces a simulated-annealing routine that repeatedly moves a subtree of tensors from one partition to another, scoring each candidate state with an estimate of time-to-solution that combines the local contraction cost with the cost of the fan-in path. On 71 benchmark circuits derived from quantum programs, the directed version of this routine found the cheapest contraction path in 51 cases; averaged over all benchmarks, it reached a computational cost of $6.6\times10^{21}$, compared with $1.3\times10^{22}$ for the comparison hyperoptimizer and $7.3\times10^{27}$ for the serial baseline. The same refinement also lowered peak memory cost by an average factor of about 8 relative to a naive partitioning.

What carries the argument

The load-bearing object is the contraction tree with a partition-accepting embedding, meaning each partition corresponds to a subtree whose leaves are exactly that partition's tensors. The distributed cost functional (3.5), stated above, is what carries the argument: it turns a partition assignment into a single number that the annealing run minimizes. The elementary move is a subtree shift: choose a subtree in a source partition, reassign its leaf tensors to a destination partition, and rebuild the two affected local contraction paths plus the inter-node reduction path. The acceptance probability uses the logarithm of the cost ratio, $\exp(-\log(c_{\mathrm{new}}/c)/T)$, which makes the algorithm insensitive to the absolute scale of costs. The directed selection objective $|T_{\mathrm{src}}|+|T_{\mathrm{dst}}|-|T_{\mathrm{result}}|$ estimates how much memory is saved by merging the moved piece with the destination partition's current root tensor.

What would settle it

Measure wall-clock time for the same benchmark circuits on a distributed cluster at partition counts well above 64, say 512 or 1024, and check whether the ordering of methods by the paper's cost metric still matches the ordering by actual time; if the directed-annealing partition stops being fastest, or the metric and the clock disagree, the central claim is falsified.

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Extended reading notes

Core claim

The central claim is that partition quality, judged by an operational-cost estimate of time-to-solution, can be improved substantially by local annealing-driven moves that reassign subtrees of the contraction tree between partitions. The objective used for scoring is the distributed cost $$\mathrm{con}_{\mathrm{dist}}(\mathcal B,K)=\max_{k\in K}\left\{\mathrm{con}(\mathcal B_k)+\sum_{v\in \mathrm{path}_k}\left($2^{{\mathrm{vc}}$(v)}+\min_{c\in \mathrm{children}(v)}\mathrm{comm}(c)\right)\right\},$$ which takes the maximum over partitions of the partition's internal contraction cost plus the fan-in path cost to the root. A move selects a subtree inside a source partition and shifts its leaf tensors to a destination partition, then rebuilds the local contraction paths and the reduction path; the directed variant chooses the destination with a greedy objective based on the size of the tensor resulting from contracting the moved piece with the destination root. With this machinery the authors report an average 8-fold reduction in computational and memory cost over a naive partitioning and better average cost than the hyperoptimizer baseline, with the directed variant achieving the lowest cost in 51 of the 71 circuits.

Load-bearing premise

The comparison rests on the assumption that the cost formula used for optimization, which ignores communication costs and takes the maximum over partitions of local cost plus fan-in cost, predicts real wall-clock time; this was validated on only ten contractions at 64 partitions.

Editorial extensions

If this is right

  • On quantum-circuit workloads of the kind collected in the benchmark suite, partition refinement alone can bring distributed tensor contraction several orders of magnitude below a serial greedy contraction path.
  • Because the directed annealing variant wins 51 of 71 circuits, the method is a strong default for unstructured or moderately structured circuits, while highly structured circuits may still favor the comparison hyperoptimizer.
  • The average memory reduction means the same approach can make larger contractions feasible within a fixed per-node memory budget.
  • The strong linear correlation between the cost metric and measured wall-clock time (Pearson $r=0.998$ on ten contractions at 64 partitions) supports using operational cost as a proxy for time-to-solution in distributed settings.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same subtree-shift annealing could be layered on top of slicing-based parallelism; the paper notes slicing was deliberately not used, so combining the two strategies is an untested but natural next step.
  • Because the acceptance probability is scale-invariant in the cost ratio, the method may transfer to larger networks without re-tuning temperature ranges.
  • The directed objective currently uses a greedy local path finder; swapping in a stronger contraction-order heuristic inside the partitions is a testable way to see whether the reported gains grow.
  • The cost metric omits communication costs by design, so at very high partition counts, where inter-node traffic could dominate, explicitly adding the communication term to the objective is the natural extension and would be needed to preserve the ranking.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper proposes two simulated annealing-based refinements for partitioning tensor networks in a distributed-memory contraction setting, with the goal of minimizing time-to-solution. The method starts from a KaHyPar partition and iteratively shifts subtrees between partitions, using either a random target selection (naive SA) or a directed objective (directed SA). The cost model is a distributed contraction cost defined in Eq. (3.5), a max over partitions of local cost plus fan-in cost, with communication costs neglected. The methods are compared against a serial baseline, KaHyPar without refinement, and Cotengra's slicing-based HyperOptimizer across a suite of MQT Bench circuits, reporting cost ratios, memory ratios, and absolute theoretical costs. The abstract claims an 8x average reduction in computational and memory cost compared to a naive partitioning.

Significance. If the central comparison were sound, the paper would make a useful contribution to HPC tensor network contraction by introducing a distributed-aware cost metric and a heuristic refinement of generic hypergraph partitioning. The paper has strengths: it proposes a concrete cost model for distributed contraction, validates that model against wall-clock time on a small subsample, and ships a reproducible algorithmic framework. However, the headline comparison with Cotengra is undermined by an inconsistent cost objective: the SA methods are scored with a parallel-time metric while Cotengra is scored with a total-serial-flops metric on sliced networks. This inconsistency directly affects the reported 51-of-71 circuit wins and the aggregate cost comparison. The experimental protocol also selects per-circuit hyperparameters (number of partitions/slices) by sweeping and averaging over only two runs, which inflates the apparent advantage. The validation of the cost metric is limited to 10 runs at a single partition count. These issues are load-bearing for the claim that the proposed method outperforms the state of the art.

major comments (4)
  1. The comparison between the partitioning methods and Cotengra is not apples-to-apples. Section 5.2 states that the cost for Cotengra was calculated using Eq. (3.2) on a sliced tensor network, assuming all slices contract in parallel. Eq. (3.2) is a serial total-flop count (a sum over all internal tree nodes), whereas the partitioning methods are scored with Eq. (3.5), which is a max over partitions and is explicitly a time-to-solution estimate. With 2 to 8 sliced legs, the number of slices ranges from 4 to 256, so the serial sum can exceed a parallel-time estimate by up to about 256x. The aggregate costs (6.6e21 vs 1.3e22) and the 51-of-71 circuit count are therefore not robust until the Cotengra baseline is recomputed with the same parallel-time objective (e.g., max over slices plus a reduction cost) or both arms use the same serial cost.
  2. The validation of the cost metric as a predictor of time-to-solution is thin. Figure 5.1 shows a high correlation (Pearson r = 0.998) but only for 10 circuit contractions, all with 64 partitions. The main experiments in Section 5.3.2 span partition counts from 4 to 256 across 71 circuits. The paper asserts that communication costs are negligible (Section 3.3) without empirical support; at larger partition counts, communication may dominate and break the linear relationship. A wider validation across partition counts and circuit sizes is needed to support the claim that the theoretical cost improvements translate to runtime improvements.
  3. The experimental protocol selects the number of partitions (or sliced legs) per circuit by sweeping over {4,8,16,32,64,128,256} (and {2,...,8} for Cotengra) and reporting the best cost. This is a per-circuit hyperparameter selection that favors methods with more flexibility; averaging over only two runs does not assess the variance of this selection. The paper should either present results for a fixed partition count as well, or report the sensitivity of the headline conclusions to the chosen partition counts.
  4. The abstract's claim of an '8x average reduction in computational cost and memory cost compared to a naive partitioning' is not substantiated by the results as written. The results are normalized against a serial baseline in Figures 5.3 and 5.4, and the absolute comparison in Figure 5.5 is against Cotengra and serial, not against a 'naive partitioning' baseline. The 8x number does not appear anywhere in the results section, so the headline claim is unsupported.
minor comments (5)
  1. The definition of the edge set E uses tuple pairs with a dimension equality condition, but the notation for the dummy vertex and its dimensions is not fully specified; a short clarification would help.
  2. In Eq. (3.5), the notation con(Bk) is used without an explicit definition; since con can be conserial or conpar, it should be stated which one is intended in this context.
  3. For the Cotengra HyperOptimizer comparison, the paper should state whether default settings were used and report the sliced leg dimensions that were selected in the sweep, since this affects the number of slices and the cost.
  4. The manuscript contains several typographical errors, including 'P ar titioning' in the title, 'F unding' in the footnote, and 'T est' in a section heading; these should be corrected.
  5. In Table 5.1, the entry for 'groundstate large' reads '14 252' which may be a formatting issue; please check the tensor count for that circuit.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the paper's results are empirical benchmarking outcomes against an independently validated cost metric and external baselines, with no load-bearing self-citation or definitional reduction.

full rationale

The paper's contribution is an optimizer for a well-defined cost model, not a derivation of a result from its own output. The distributed cost metric (3.5) is introduced from graph-theoretic concepts with reference to O'Gorman [26] and then independently validated against measured wall-clock time in Section 5.3.1: 'The Pearson correlation coefficient is 0.998' for 10 circuit contractions at 64 partitions. The simulated-annealing methods minimize this cost, and the reported 'lowest computational cost in 51 of the 71 investigated circuits' is a benchmark outcome compared against external methods (Cotengra's HyperOptimizer and a KaHyPar-based baseline), not a quantity forced by construction. The per-circuit partition-count sweeps over {4,8,16,32,64,128,256} and Cotengra's sliced-leg sweep over {2,3,4,5,6,7,8} are tuning procedures applied symmetrically to all methods, so no fitted parameter is renamed as a prediction. There is no load-bearing self-citation chain: the central external references, such as [10] and [26], are not by the present authors, and no uniqueness theorem or prior-work assumption is invoked to forbid alternatives. One benchmark-consistency caveat exists but is not circular: the paper states that for Cotengra, 'The cost was calculated using (3.2) on a sliced tensor network, assuming that all slices can be contracted in parallel,' while Eq. (3.2) is the serial sum over all internal tree nodes and partitioning methods are scored with the parallel/critical-path cost (3.5). This may skew the aggregate 6.6e21 vs 1.3e22 comparison, but it is an apples-to-oranges comparison issue, not a reduction of the paper's claims to its own inputs. Accordingly, the circularity score is 0.

Assumptions & free parameters 6 free parameters · 5 assumptions · 0 invented entities

The central claim rests on the SA hyperparameters (not reported) and on the cost model (3.5) with its simplifying assumptions about communication. The per-circuit selection of partition count and slice count is a tuning step that affects all compared methods equally but inflates the absolute improvement over a fixed configuration.

free parameters (6)
  • Initial temperature T0 of simulated annealing
    Determines acceptance probability in Eq. (4.2); values are not reported, so a re-implementation must tune them per problem.
  • Final temperature Tf of simulated annealing
    Sets cooling endpoint in Eqs. (4.3)-(4.4); not reported.
  • Steps per processor Nsteps
    Controls number of SA moves per temperature step (Algorithm 4.1); not reported.
  • Restart threshold
    Number of iterations without improvement before restarting from best (Algorithm 4.1); not reported.
  • Number of partitions per circuit = chosen per circuit from {4,8,16,32,64,128,256}
    Selected as the value that gave the best cost for each circuit, a form of fitting to the benchmark (§5.2).
  • Number of sliced legs for Cotengra = chosen per circuit from {2,3,4,5,6,7,8}
    Selected as best per circuit for the comparison baseline (§5.2).
assumptions (5)
  • domain assumption Communication costs are negligible compared with tensor contraction costs.
    Stated in §3.3: 'communication costs are not included in theoretical calculations as empirical results indicate that these costs are far smaller than the tensor contraction costs.' This underpins the cost model (3.5).
  • domain assumption Only one tensor needs to be communicated per inter-node contraction, and the smaller child tensor is chosen.
    Assumed in the definition of comm(c) in §3.3; affects the fan-in cost estimate.
  • domain assumption The cost metric (3.5) using max over partitions plus critical-path fan-in approximates parallel time-to-solution.
    Validated only on 10 contractions at 64 partitions (§5.3.1, Fig. 5.1); used for all comparisons.
  • domain assumption Contraction paths found by Greedy/RandomGreedy within partitions are representative of achievable costs.
    The reported improvements depend on the local contraction order quality; §4.4 acknowledges using a 'very naive contraction order finder'.
  • standard math Standard mathematical definitions from O'Gorman [26] for congestion and cost.
    Equations (3.1)-(3.4) are taken from prior work; not re-derived.

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Cite this review

Pith. "Pith review of Optimizing Tensor Network Partitioning using Simulated Annealing." pith.science (2026). https://pith.science/paper/ZFMWR4NJ

@misc{pith2026250720667,
  author       = {Pith},
  title        = {Pith review of: Optimizing Tensor Network Partitioning using Simulated Annealing},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/ZFMWR4NJ}},
  note         = {Machine review of arXiv:2507.20667}
}
abstract

Tensor networks have proven to be a valuable tool, for instance, in the classical simulation of (strongly correlated) quantum systems. As the size of the systems increases, contracting larger tensor networks becomes computationally demanding. In this work, we study distributed memory architectures intended for high-performance computing implementations to solve this task. Efficiently distributing the contraction task across multiple nodes is critical, as both computational and memory costs are highly sensitive to the chosen partitioning strategy. While prior work has employed general-purpose hypergraph partitioning algorithms, these approaches often overlook the specific structure and cost characteristics of tensor network contractions. We introduce a simulated annealing-based method that iteratively refines the partitioning to minimize the total operation count, thereby reducing time-to-solution. The algorithm is evaluated on MQT Bench circuits and achieves an 8$\times$ average reduction in computational cost and an 8$\times$ average reduction in memory cost compared to a naive partitioning.

Figures

Figures reproduced from arXiv: 2507.20667 by the authors.

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Pith tools

Reviewed August 6, 2026 · model on record in the stance chip above.