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Optimizing sparse quantum state preparation with measurement and feedforward

T0 review · 3 major / 6 minor · reviewed 2026-08-05 · deepseek-v4-flash

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Pith's one-line read Two circuits prepare arbitrary sparse quantum states; with measurement and feedforward the depth drops to O(n) using O(d) ancillas.

desk verdict A plausible new depth-ancilla trade-off for sparse QSP, but the O(n)-depth MaF theorem is not yet proven: fan-out reuse and BST uncomputation both need repair. read the letter →

arxiv 2508.21346 v1 pith:EB5EKWKT submitted 2025-08-29 quant-ph

Yao-Cheng Lu , Han-Hsuan Lin This is my paper · ORCID
classification quant-ph
keywords quantumstatepreparationsparsestatescircuitdepthancillaqubitsmeasurementandfeedforwardfan-outgateone-hotencodingpermutation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Quantum state preparation is often the bottleneck in quantum algorithms, and for states with only d nonzero amplitudes the question is how much shallower a circuit can be when ancilla qubits are limited. This paper answers that question with two constructions. The first prepares any n-qubit d-sparse state in depth O(n log d), size O(dn), and O(d) ancillas without mid-circuit measurement. The second adds measurement and classical feedforward to reach depth O(n), independent of d, with the same size and ancilla count. The result is that, for highly sparse states, preparation depth no longer scales with the sparsity parameter at all.

What carries the argument

The load-bearing object is the MaF (measurement and feedforward) class of circuits and, inside it, the constant-depth quantum fan-out gate: a fan-out over k target qubits is realized by a layer of Hadamards and CNOTs, a mid-circuit measurement, a classical XOR computation, and a final layer of X/Z gates. Because the algorithm needs fan-out only on the one-hot register and because a parity-controlled X gate is just a fan-out conjugated by Hadamards (Corollary 1), every parallel step in the one-hot encoding, permutation, and garbage elimination can be compressed to constant depth. The one-hot encoding and the binary-search-tree encoding of the target basis states are what let the n sequential

What would settle it

Take a concrete instance, e.g. n=5, d=4, and explicitly decompose every MaF fan-out gate used in Algorithms 4, 6, and 7 into the constant-depth measurement circuit of [37], tracking qubit identities and resets after each of the n parity-controlled X steps. If the uncomputation of any fan-out leaves the ancillas entangled with the data register, or if resetting/reusing the measured ancillas between steps requires more than O(d) total ancillas or adds more than constant depth, then the size-depth-ancilla claims of Theorem 2 fail on that instance.

Watch

Extended reading notes

Core claim

Central claim (Theorem 2): any n-qubit d-sparse state can be prepared in the measurement-and-feedforward (MaF) class with size O(dn), depth O(n), and O(d) ancillas. The circuit prepares the d amplitudes on ⌈log d⌉ qubits, expands them to a one-hot encoding on d ancillas, permutes each amplitude to its target basis state via one parity-controlled X gate per output qubit, and uncomputes the one-hot data through a recorded binary search tree. Lemma 1 makes OR-controlled X equal to parity-controlled X on one-hot controls; parity-controlled X is a fan-out conjugated by Hadamards. Using constant-depth MaF fan-out gates everywhere removes d from the depth; without MaF, the same steps give depth O(n

Load-bearing premise

The construction assumes that a MaF fan-out gate can be applied twice—compute and uncompute—without leaving residual garbage or exceeding O(d) ancillas, and that the measured ancillas can be reused across the n sequential parity gates in Step 3; this is asserted in Algorithms 4, 6, and 7 but never proven.

Editorial extensions

If this is right

  • Any n-qubit d-sparse state can be prepared in depth O(n) with O(d) ancillas, so the depth is linear in n and independent of d.
  • For d much smaller than 2^n, the O(dn) gate count is near-linear in n, far below the Θ(2^n) gates required for general state preparation.
  • Compared with the constant-depth MaF construction in [33], this algorithm shrinks circuit size from O(d^2 log n) to O(dn) and ancillas from O(d^2 log n) to O(d), trading constant depth for linear depth.
  • The non-MaF construction (Theorem 1) gives the same size and ancilla counts with depth O(n log d), covering hardware without mid-circuit measurement and feedforward.
  • Because many quantum algorithms that call state preparation already run at O(n) depth, an O(n)-depth sparse preparer can be inserted without making preparation the bottleneck.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same four-step skeleton could generalize to other structured state families (for example, states whose nonzero positions are produced by a classical circuit), wherever an efficient controlled permutation is available; that generalization is not in the paper.
  • A natural testable extension is to compile Algorithms 4, 6, and 7 for a small instance, say n=5 and d=4, into native gates, and check whether the MaF fan-out gates can indeed be reused across all n parity steps with only O(d) ancillas and constant reset cost.
  • The paper leaves open whether depth Ω(n) is necessary for MaF-based sparse preparation with O(d) ancillas; a matching lower bound would make the O(n) depth of Theorem 2 tight.
  • If the fan-out reuse assumption survives, the design suggests a broader recipe for flattening any QSP bottleneck that is fan-out-like: expand to a one-hot register, permute in parallel, then uncompute—which is the paper's insight applied beyond the specific states considered here.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The paper proposes two sparse quantum state preparation (SQSP) algorithms for arbitrary n-qubit d-sparse states. The first uses O(d) ancilla qubits, circuit size O(dn), and depth O(n log d). The second additionally uses mid-circuit measurement and feedforward (MaF) to reduce the depth to O(n) while keeping size O(dn) and O(d) ancilla. The construction proceeds through four steps: low-depth GQSP on ⌈log d⌉ qubits, one-hot encoding of the d basis indices into ancilla registers, a permutation step that maps |i⟩ to |q_i⟩ using OR- or parity-controlled X gates, and a garbage elimination step that resets the one-hot ancilla using a binary-search-tree recording. Theorems 1 and 2 state the resulting complexity bounds.

Significance. If Theorem 2 is correct, it is a meaningful improvement: it achieves depth O(n) independent of d with only O(d) ancilla, whereas the prior MaF-based construction of [33] uses Θ(1) depth but O(d² log n) size and ancillas, and non-MaF sparse preparation methods typically use either more depth or many more ancillas. The paper is also transparent in using external results (low-depth GQSP [40], constant-depth fan-out [37], Toffoli decompositions [38]) as assumptions rather than deriving them internally, and no fitted parameters are involved. However, the central claim depends on a reusable, clean measurement-based fan-out gadget and on explicit uncomputation protocols, neither of which is established in the manuscript. The result is therefore plausible but not yet rigorously supported.

major comments (3)
  1. [Section III.B, Algorithms 2/3/4, Eq. (17)] The one-hot encoding is implemented for a B register of size d, but the CSWAP indices run up to 2^{⌈log d⌉}-1. For d not a power of two, these indices exceed the register. Example: d=5, ⌈log d⌉=3, Algorithm 2 with j=1, i=1 references B(4) and B(6), but B(6) does not exist. Since the theorem claims arbitrary d, the algorithm is invalid as written for non-power-of-two d. Either the algorithm must be modified to touch only indices <d (with a proof that the restricted swap network still produces the correct one-hot state), or the theorem must be restricted.
  2. [Section II.B Theorem 3; Section III.B/C, Algorithms 4, 6, 7] The measurement-based fan-out gate of [37] is treated as a reusable unitary operation whose ancillas can be reused across multiple calls within the O(d) ancilla budget. This is never proved. In Algorithm 4 the same FANOUT is applied twice to the same C register; in Algorithm 6 it is invoked in n consecutive parity gates; and in Algorithm 7 it is called in every layer. A mid-circuit-measurement gadget is not automatically a unitary on data+ancilla and may consume its ancillas. If each invocation requires fresh ancillas, Step 3 alone needs Θ(nd) ancillas, and if each invocation requires resetting ancillas to |0⟩, that reset cost must be counted in the depth. A formal lemma stating the exact action of the gadget on all qubits and specifying the reset/feedforward protocol is load-bearing for Theorem 2.
  3. [Section IV.D.3, Eq. (21), Algorithm 7] The reset of the C register is asserted to be 'similar to Step 4.1', but the recording operations are not self-inverse. For the first branch, the sequence X(C(0)); CSWAP(A(j), C(0), C(1)) maps |00⟩ to |10⟩ when A(j)=0 and to |01⟩ when A(j)=1. Applying the same sequence to the recorded state |01⟩ with A(j)=1 maps it to |11⟩, not back to |00⟩; the inverse order CSWAP then X is required. The paper does not give the explicit uncompute circuit or its depth. Without a correct uncompute, the C register is not reset and the final state is not |ϕ⟩|0⟩⊗4d. This affects both Theorem 1 and Theorem 2.
minor comments (6)
  1. [Algorithm 4, line 5] The CSWAP line reads CSWAP(C(j), ...) but it should almost certainly be CSWAP(C(i), ...) to match the loop variable and Algorithm 3.
  2. [Algorithm 4 output] The output line writes `|ei⟩⊗d`; it should be `|ei⟩` (a single one-hot state).
  3. [Theorem 2 statement] Typo: 'O(d) acilla qubits' should be 'ancilla qubits'.
  4. [Section III.D/Table III] The size of the garbage-elimination step is reported inconsistently: Algorithm 8 has d CNOTs, Table III says size O(d), Section III.D.2 says size O(n), and the proof of Theorem 1 says size O(dn). These should be reconciled.
  5. [Lemma 2 heading] Typo: 'n-Toffoli gat' should be 'n-Toffoli gate'.
  6. [Definition 2] The MaF model should explicitly specify whether reinitializing a measured qubit to |0⟩ is allowed as part of a classical layer or quantum layer, and how its cost is accounted. This is relevant to the fan-out reuse issue.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: Theorem 2 is a composition of external results (low-depth GQSP [40], MaF fan-out [37], Toffoli constructions [38], parity/fan-out duality [41]); the flagged fan-out ancilla-reuse issue is an omitted-proof correctness risk, not a circular reduction.

full rationale

I walked the derivation chain of Theorems 1 and 2, including Algorithms 2–8 and the proofs in Section III.E. Every complexity claim is assembled from external theorems that are taken as assumptions, not derived in this paper: the GQSP subroutine is Theorem 5 from [40], the constant-depth MaF fan-out is Theorem 3 from [37], the n-Toffoli lemmas are from [38], and the parity/fan-out duality is from [41]. None of these is a self-citation of the present authors, and none reduces to the paper's own target quantity. The problem input S defines only the target sparse state; the output states are explicitly checked against Eq. (2). There are no fitted parameters, no numerical data are predicted from fitted values, and no claimed result is defined in terms of the quantity it is supposed to establish. I also considered the passages flagged by the skeptic: the repeated FANOUT calls in Algorithm 4 (lines 3 and 7), Algorithm 7 (lines 16 and 20), and the unproven 'method is similar to Step 4.1' reset claim in Section IV.D.3. These are genuine omissions in the proof that the MaF fan-out gadget can be reused as a clean reversible operation within the O(d) ancilla budget. However, that is a correctness gap or missing proof, not circularity: the fan-out gadget is cited from external work, not constructed from the paper's own conclusions, and the paper does not fit any parameter or rename any known result to produce its complexity bounds. Under the stated external theorems, the derivation is self-contained. The honest finding is no significant circularity; score 0.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

The algorithm has no free parameters and introduces no new entities. It depends on three external theorem-level assumptions and one ad hoc assumption about register sizing.

assumptions (4)
  • domain assumption Low-depth GQSP algorithm (Theorem 5 of [40]) prepares an arbitrary n-qubit state in depth O(n) with O(2^n) ancilla; on log d qubits this is depth O(log d), size O(d), ancilla O(d).
    Relied on in Step 1 (Section III.A) without proof.
  • domain assumption Constant-depth fan-out gate via MaF (Theorem 3 of [37]) implements an n-qubit fan-out with n-1 ancilla and a single measurement layer; it is a unitary operation that can be uncomputed by re-applying the same circuit.
    Relied on in Steps 2-4 with MaF; the uncomputation part is not proven in the paper.
  • domain assumption Standard gate decompositions: n-Toffoli with one ancilla has depth O(log n) and size O(n) (Lemma 3 of [38]); Fredkin and controlled-Ry have constant depth.
    Used in OR-C-X and CSWAP implementations (Section II.A).
  • ad hoc to paper The one-hot encoding construction assumes the B register has at least 2^(ceil(log d)) qubits or that d is a power of two.
    Algorithm 2 uses CSWAP indices up to 2^m - 1, but B is defined with d qubits; for non-power-of-two d the gates reference nonexistent qubits.

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Cite this review

Pith. "Pith review of Optimizing sparse quantum state preparation with measurement and feedforward." pith.science (2026). https://pith.science/paper/EB5EKWKT

@misc{pith2026250821346,
  author       = {Pith},
  title        = {Pith review of: Optimizing sparse quantum state preparation with measurement and feedforward},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/EB5EKWKT}},
  note         = {Machine review of arXiv:2508.21346}
}
abstract

Quantum state preparation (QSP) is a key component in many quantum algorithms. In particular, the problem of sparse QSP (SQSP) $\unicode{x2013}$ the task of preparing the states with only a small number of non-zero amplitudes $\unicode{x2013}$ has garnered significant attention in recent years. In this work, we focus on reducing the circuit depth of SQSP with limited number of ancilla qubits. We present two SQSP algorithms: one with depth $O(n\log d)$, and another that reduces depth to $O(n)$. The latter leverages mid-circuit measurement and feedforward, where intermediate measurement outcomes are used to control subsequent quantum operations. Both constructions have size $O(dn)$ and use $O(d)$ ancilla qubits. Compared to the state-of-the-art SQSP algorithm in arXiv:2108.06150, which allows an arbitrary number of ancilla qubits $m>0$, both of our algorithms achieve lower circuit depth when $m=d$.

Figures

Figures reproduced from arXiv: 2508.21346 by the authors.

Figure 1
Figure 1. FIG. 1. Toffoli Gate [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. FIG. 2. Fredkin Gate [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. FIG. 3. controlled-R [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (12 more)
Figure 4
Figure 4. Figure 4: FIG. 4. control-R [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: FIG. 5. A quantum multi-OR-controlled single target X [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 7
Figure 7. Figure 7: FIG. 7. Measurement-based implementation of the fan [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]
Figure 8
Figure 8. Figure 8: FIG. 8. Binary search tree with [PITH_FULL_IMAGE:figures/full_fig_p008_8.png]
Figure 9
Figure 9. Figure 9: FIG. 9. The Grover-Rudolph circuit to prepare the [PITH_FULL_IMAGE:figures/full_fig_p008_9.png]
Figure 10
Figure 10. Figure 10: FIG. 10. A simple example of one-hot encoding for [PITH_FULL_IMAGE:figures/full_fig_p009_10.png]
Figure 11
Figure 11. Figure 11: FIG. 11. An example of a circuit that performs single [PITH_FULL_IMAGE:figures/full_fig_p009_11.png]
Figure 12
Figure 12. Figure 12: FIG. 12. An example of a circuit that performs CSWAP [PITH_FULL_IMAGE:figures/full_fig_p010_12.png]
Figure 14
Figure 14. Figure 14: FIG. 14. The parity-controlled X gate can be [PITH_FULL_IMAGE:figures/full_fig_p011_14.png]
Figure 13
Figure 13. Figure 13: FIG. 13. An example circuit for implementing [PITH_FULL_IMAGE:figures/full_fig_p011_13.png]
Figure 15
Figure 15. Figure 15: FIG. 15. Binary search tree for [PITH_FULL_IMAGE:figures/full_fig_p013_15.png]
Figure 16
Figure 16. Figure 16: FIG. 16. Circuit for recording the binary search tree [PITH_FULL_IMAGE:figures/full_fig_p013_16.png]

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Pith tools

Reviewed August 5, 2026 · model on record in the stance chip above.