An Exact Branch and Bound Algorithm for the generalized Qubit Mapping Problem

Bj{\o}rnar Luteberget; Dominik Leib; Franz G. Fuchs; Giorgio Sartor; Kjell Fredrik Pettersen; Raoul Heese; Tobias Seidel

REVIEW 3 major objections 5 minor 21 references

An Exact Branch and Bound Algorithm for the generalized Qubit Mapping Problem

T0 review · 3 major / 5 minor · reviewed 2026-08-05 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

Pith's one-line read An exact branch-and-bound solver shows that dropping layering constraints can cut SWAP counts by 30% on sparse quantum hardware.

desk verdict A unified exact B&B that quantifies the cost of the layering assumption—useful, credible in direction, but the admissibility of the gate lower bound is asserted rather than proven, and the strongest empirical row rests on few solved instances. read the letter →

arxiv 2508.21718 v1 pith:RYDEVDW4 submitted 2025-08-29 quant-ph

Bj{o}rnar Luteberget , Kjell Fredrik Pettersen , Giorgio Sartor , Franz G. Fuchs , Dominik Leib , Tobias Seidel , Raoul Heese This is my paper · ORCID

classification quant-ph

keywords qubitmappingroutingbranchandboundlowerboundsSWAPgatescircuitdepthlayeringquantumcompilation

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Quantum compilers usually group gates into layers and insert SWAPs only between layers, which restricts reordering and ignores gate durations. This paper builds an exact branch-and-bound algorithm for the Qubit Mapping Problem that can either impose or relax the layering assumption while tracking gate execution times. It uses this solver to find proven optimal solutions for small circuits on linear, grid, and Y-shaped hardware graphs, and reports that on sparsely connected hardware the optimal non-layered solutions are substantially better: relative mean deviation of 6.38% in depth and 30.79% in SWAP count on the Y graph. If the lower bounds are admissible as claimed, this provides a way to measure exactly how much standard layered compilation loses and a platform for heuristic variants.

What carries the argument

Central is the search node (assignment map, unscheduled-gate set, per-qubit depth map), kept only when on the Pareto front of its state class. Expansion schedules a minimal circuit gate or a SWAP gate. The depth bound hD = max(hQ, hG) combines a per-qubit residual-time bound with a path-based bound: for each unscheduled gate, H_n(i, pi, j) estimates earliest start from hardware-path depths plus remaining gate durations and SWAP move times, minimized over paths and edge positions. For SWAP count, hS adds current SWAPs to the longest current distance minus one. Layering mode adds recursive layer indices and blocks scheduling a layer-l gate before all layer-(l-1) gates.

What would settle it

Enumerate all feasible schedules for a small instance, such as a four-qubit linear graph with three gates, and compare the formula in Eq. (11) with the true earliest start of each unscheduled gate at each search node; if any term ever exceeds the true earliest start, the lower bound is invalid and the proven-optimal claim collapses. Alternatively, solve the same instances with an independent exact method and check for a returned solution better than the algorithm's.

Watch

Extended reading notes

Core claim

The paper presents an exact branch-and-bound algorithm for the Qubit Mapping Problem. Each search node stores the current virtual-to-physical qubit assignment, the unscheduled gates, and each physical qubit's earliest completion time; dominated states are discarded via a Pareto front. Expansion schedules a minimal circuit gate or a SWAP gate, guided by lower bounds hQ, hG, and hS, which the authors claim are admissible, so the first complete schedule found is optimal. Running this solver with layering on and off, ignoring layers lowers optimal depth by 6.38% relative mean deviation on the Y graph (815/900 instances solved) and optimal SWAP count by 30.79% (59/811 solved), with smaller gains

Load-bearing premise

The guarantee of proven optimality depends on the unproved claim that every term in the path-based lower-bound formula is never larger than the true earliest time an unscheduled gate can start; if that fails, the search can prune the optimum.

Editorial extensions

If this is right

On sparsely connected hardware, the layering restriction carries a measurable, provable cost: on the Y graph the gap reaches 30.79% in optimal SWAP count.
On well-connected hardware such as a grid, layering costs little (0.09% depth relative mean deviation), so the added complexity of unlayered exact compilation is not warranted there.
Optimizing for depth also tends to reduce SWAP count because SWAP gates are long, but optimizing for SWAP count does not reliably reduce circuit depth.
Because the algorithm returns proven optima only when the lower bounds are admissible, deliberately weakening those bounds turns the same search into a fast heuristic platform.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The gap between layered and unlayered optima likely grows with graph centrality imbalance: star or heavy-hex topologies with one busy hub could show even larger losses than the Y graph, because routing through a hub forces SWAPs inside what would be a fixed layer.
The unproved admissibility of hG can be checked independently: brute-force enumeration of all feasible completions on the smallest instances would reveal whether any term in Eq. (11) ever exceeds the true earliest start of a gate.
The same state-space and Pareto-front machinery could be extended to weighted objectives on noisy qubits, turning the solver into an exact error-rate minimizer rather than a depth or SWAP proxy optimizer.
The lower bounds described here could be reused in an anytime A* variant for larger circuits, sacrificing the proven-optimal guarantee when aggressive pruning is applied.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Plainly: this is worth a serious referee. The core deliverable is not a new complexity result but a concrete, quantifiable answer to a question people usually skip—what does the fixed-layer assumption cost in exact qubit mapping. They build one branch-and-bound framework that can toggle layering, gate durations, and depth-vs-SWAP objective, and they show on small sparse graphs that releasing the layer constraint improves proven-optimal solutions: on the Y graph, depth improves by 6.38% RMD (815/900 solved) and SWAP count by 30.79% on the 59/811 instances where both solved. The effect is consistent in direction across topologies and objectives, which lends it credibility.

The search framework is coherent: best-first expansion with Pareto dominance pruning per state, qubit-based and gate-based lower bounds, and a clean extension to SWAP-count minimization. The bounds are individually plausible. The comparison is between two optimal solutions of well-defined model variants, not a fitted heuristic, so the empirical gap is not circular.

The load-bearing weakness is that admissibility of hG/hD is asserted, not proved. One short paragraph says H_n(i,pi,j) is a lower bound on the earliest start, but there is no theorem, no proof, and no independent exact cross-check. Since the search is best-first and prunes dominated nodes, one underestimate in any H_n term could let a suboptimal goal pop first and return a non-optimal mapping. I am not saying the bound is wrong—the terms are reasonable—but “proven optimal” should be backed by either an admissibility proof or a sanity check against a different exact solver on small instances.

Second soft spot: the headline empirical claim in the Y/SWAP row rests on 59 of 811 solved instances, so survivor bias is real. The paper does report the solved counts, which is good, but the RMD is computed only on jointly solved cases. Also, the implemented layering mode is weaker than the standard grouped QMP, so the reported cost of layering is a lower bound on the real cost. And the introduction promises a comparison with existing compilers that the results section never delivers.

Who is this for? People working on exact compilation methods or benchmark studies for QMP. The main finding—that layer relaxation matters most on sparse, high-centrality graphs—is useful even if absolute numbers shift. I would send it to peer review. It needs an admissibility proof and an independent check before the optimality claim is bulletproof, but the problem is well posed and the framework is reusable.

Referee Report

3 major / 5 minor

Summary. The paper presents an exact branch-and-bound algorithm for a generalized Qubit Mapping Problem. Search states are partial schedules of circuit gates and SWAP gates; the algorithm maintains a Pareto front over states with the same assignment and unscheduled-gate set, and expands the open node with the smallest lower bound. Three lower bounds are introduced: hQ based on remaining qubit serialization times, hG based on path/router lower bounds for individual gates, and hS based on the longest current hardware distance among unscheduled gates. The algorithm can optimize depth, SWAP count, or a weighted combination, and can enforce or relax a layered schedule structure. The experiments compare layered versus non-layered optimal solutions on random circuits over Linear, Grid, and Y hardware graphs with 4–6 qubits, reporting that relaxing layering reduces depth and SWAP counts, most strongly on the Y graph. The central claims are that the algorithm returns proven optimal solutions and that the non-layered formulation materially improves compilation quality on sparse hardware.

Significance. If the lower-bound claims are correct, the paper contributes a flexible exact framework for small QMP instances and gives concrete, well-defined evidence about the cost of the layered-schedule abstraction. The study is designed without fitted parameters, and the layered-versus-non-layered comparison compares two optimal solutions of well-defined model variants, so the reported gaps are not forced by construction. However, the optimality guarantee rests entirely on the admissibility of hG, which is asserted but not proved, and no independent exact solver or brute-force check is used to confirm the claimed optimal values. The significance is therefore conditional: the conceptual framework is valuable, but the paper's headline claims need a rigorous admissibility proof and external validation before they are fully supported.

major comments (3)

[§3.3, Definitions 4–5, Eqs. (11)–(13)] The admissibility of hG is asserted but not proved. It is stated that H_n(i,π,j) in Eq. (11) is a lower bound on the earliest start of gate g_i, and that taking the minimum over paths/edges in Eq. (12) preserves this property, but no lemma or theorem is provided. Since Algorithm 1 is best-first and returns the first goal node popped, any single overestimate of an H_n term can cause a suboptimal solution to be returned. The further restriction in Eq. (12) to 'first unscheduled common gates' is also asserted without proof. Please supply a formal proof of each step, and also state and prove the conditions under which hS in Eq. (14) is admissible for the SWAP-count objective.
[§4, Table 3 and overall experiments] All reported 'optimal' solutions come from the same implementation with no independent verification. A subtle bug or an overestimating term in hG would invalidate both the algorithmic claim and the layered-versus-non-layered comparison. I recommend cross-checking the implementation against an independent exact method, e.g. the MILP formulation of [14] for the layered mode and brute-force or SAT enumeration for small non-layered instances (at least n≤4 with small depth), and reporting per-variant convergence rates and timeouts.
[§4.2, Table 3] Table 3 is difficult to parse: six columns are defined but some rows appear to contain only four or five numeric entries. In particular, the Y-graph / num-SWAPs row must state clearly whether N_S=811 and N==59 or N=811 and N_S=59. If only 59 instances are used for the reported RMD=30.79%, the empirical improvement claim is based on a small and potentially nonrepresentative subset; if N_S=811, this concern is largely resolved but the table must still be unambiguous. Also clarify how RMD handles cases where the layered objective value y_L is zero.

minor comments (5)

[Abstract] Typo: 'can find find proven optimal solutions' should read 'can find proven optimal solutions'.
[§3.4] Grammar: 'The Pareto front value domain in the algorithm will must then be extended' should be 'will then be extended'.
[§4 introduction] The text promises 'comparing our methods to existing compilers', but Section 4 only compares the layered and non-layered variants of Algorithm 1. Either add such comparisons or adjust the wording.
[§4.1] For reproducibility, please provide the random seeds used for circuit generation or make the instance set and implementation publicly available. The paper currently states that the implementation is in Python but gives no code or data link.
[Figures 4 and 5] The parity plots omit non-converged instances; it would be helpful to report the number of instances shown in each panel (or in the caption) so that the visual comparison can be interpreted alongside Table 3.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: lower bounds are constructed from problem data and the layered/non-layered comparison is an empirical comparison of two defined model variants.

full rationale

The paper's derivation chain is self-contained and non-circular. The branch-and-bound lower bounds hQ, hG, hD, hS (Eqs. 10, 12, 13, 14) are defined directly from circuit durations, gate precedences, hardware distances, and current node depths; no parameter is fitted to the instances or to the reported optima, and no result is imported from the authors' prior work (the paper cites only external literature). The claim that the heuristic is admissible is a mathematical assertion ('If h(n) is always a lower bound, the search algorithm will be admissible...', Sec. 3.3), but the admissibility of Eq. (11) is not proven in the text. That is a validation/correctness gap, not circularity: the bound is not defined in terms of the algorithm's output, and the optimality claim does not reduce to an input by construction. The layered-versus-non-layered comparison is also not circular: the layered feasible set is a subset of the non-layered feasible set, so non-dominated improvement is mathematically expected, but the reported magnitudes (RMD values in Table 3) are empirical results from solving two well-defined model variants with the same exact search, not quantities forced by the definition of the heuristic. No self-citation is load-bearing, and there is no renaming of a known result as a new derivation. The only caveat, which affects correctness rather than circularity, is that the admissibility of hG is asserted without formal proof and without independent exact-solver cross-checks; if any term in Eq. (11) overestimates the true earliest start time, the 'proven optimal' claims could be invalid. This does not make the argument circular.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

The central contribution rests on the usual QMP modeling assumptions (circuit as ordered two-qubit gates with durations, hardware as a graph with unit-cost SWAPs) plus three paper-specific premises: the admissibility of the custom lower bounds, the exactness of the Pareto-front dominance pruning, and the chosen representation of layering as a pure ordering constraint. Gate and SWAP durations in Table 1 are measured from IBM Kyoto via Qiskit and scaled by 1/16, a unit convention rather than a fitted parameter. The objective weights wD and wS (Eq. 15) are set to (1,0) or (0,1) in the experiments, not fitted. No invented physical entities are introduced.

assumptions (5)

domain assumption Circuit is a fixed sequence of two-qubit gates with durations; single-qubit gates are folded into the next two-qubit gate's duration, and final single-qubit gates are ignored
Section 4.1; standard abstraction (cited [14]) but it skews makespan for circuits ending in single-qubit gates, a systematic bias in all reported depths.
standard math Precedence among gates is the total order of the circuit sequence restricted to shared qubits
Section 2, Eq. (1) and Definition 2 (Eq. 6); standard partial-order model for scheduling, also used for the recursive lower bound delta(i).
ad hoc to paper Admissibility of the lower bounds hQ (Eq. 10), hG (Eqs. 11-12), and hS (Eq. 14)
Asserted with informal justification in Section 3.3; no formal proof. The entire exactness guarantee ('proven optimal') rests on these bounds never underestimating the optimum.
ad hoc to paper Pareto-front state pruning is dominance-safe for the depth and SWAP-count objectives
Section 3.2 (Algorithm 3); equivalence classes require the same assignment and the same unscheduled gate set, and the paper argues dominance informally, without proof. For the SWAP objective it says the Pareto value domain 'must then be extended' with s_n, also without proof.
domain assumption Layering restriction is modeled only as an ordering constraint by layer index L(i)
Section 3.5 (Eq. 16); this differs from the standard layered QMP (same time slot per layer, SWAPs only between layers), so the measured layering gap is a lower bound on the standard layering cost.

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Cite this review

Pith. "Pith review of An Exact Branch and Bound Algorithm for the generalized Qubit Mapping Problem." pith.science (2026). https://pith.science/paper/RYDEVDW4

@misc{pith2026250821718,
  author       = {Pith},
  title        = {Pith review of: An Exact Branch and Bound Algorithm for the generalized Qubit Mapping Problem},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/RYDEVDW4}},
  note         = {Machine review of arXiv:2508.21718}
}

read the original abstract

Quantum circuits are typically represented by a (ordered) sequence of gates over a set of virtual qubits. During compilation, the virtual qubits of the gates are assigned to the physical qubits of the underlying quantum hardware, a step often referred to as the qubit assignment problem. To ensure that the resulting circuit respects hardware connectivity constraints, additional SWAP gates are inserted as needed, which is known as the qubit routing problem. Together, they are called the Qubit Mapping Problem (QMP), which is known to be NP-hard. A very common way to deal with the complexity of the QMP is to partition the sequence of gates into a sequence of gate groups (or layers). However, this imposes a couple of important restrictions: (1) SWAP gates can only be added between pairs of consecutive groups, and (2) all the gates belonging to a certain group have to be executed (in parallel) in the same time slot. The first one prevents gates to be re-arranged optimally, while the second one imposes a time discretization that practically ignores gate execution time. While this clearly reduces the size of the feasible space, little is still known about how much is actually lost by imposing a fixed layering when looking at the minimization of either the number of SWAPs or the makespan of the compiled circuit. In this paper, we present a flexible branch and bound algorithm for a generalized version of the QMP that either considers or ignores the gate layering and the gate execution time. The algorithm can find find proven optimal solutions for all variations of the QMP, but also offers a great platform for different heuristic algorithms. We present results on several benchmark sets of small quantum circuits, and we show how ignoring the layering can significantly improve some key performance indicators of the compiled circuit.

Figures

Figures reproduced from arXiv: 2508.21718 by the authors.

**Figure 2.** Two different ways of drawing of a simple circuit [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** Exemplary representations of the three hardware graphs used, with six physical qubits [PITH_FULL_IMAGE:figures/full_fig_p011_3.png] view at source ↗

Figures from the paper (2 more)

**Figure 4.** Figure 4: Parity plots for the depth objective for the three hardware graphs Linear, Grid and Y. [PITH_FULL_IMAGE:figures/full_fig_p013_4.png]

**Figure 5.** Figure 5: Parity plots for the number of SWAPs objective for the three hardware graphs Linear, [PITH_FULL_IMAGE:figures/full_fig_p014_5.png]

Discussion (0). Continue with ORCID to comment.

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Pith tools

Reviewed August 5, 2026 · model on record in the stance chip above.

[1] [14]

Optimal qubit as- signment and routing via integer programming

Giacomo Nannicini, Lev S Bishop, Oktay G¨ unl¨ uk, and Petar Jurcevic. Optimal qubit as- signment and routing via integer programming. ACM Transactions on Quantum Computing , 4(1):1–31, 2022

work page 2022

[2] [1]

Complexity-theoretic foundations of quantum supremacy experiments

Scott Aaronson and Lijie Chen. Complexity-theoretic foundations of quantum supremacy experiments. In Proceedings of the 32nd Computational Complexity Conference , CCC ’17, Dagstuhl, DEU, 2017. Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik

work page 2017

[3] [2]

Depth-Optimal Quantum Circuit Placement for Arbitrary Topologies

Debjyoti Bhattacharjee and Anupam Chattopadhyay. Depth-optimal quantum circuit place- ment for arbitrary topologies. arXiv preprint arXiv:1703.08540 , 2017. 15

work page Pith review arXiv 2017

[4] [3]

On the complexity of quantum cir- cuit compilation

Adi Botea, Akihiro Kishimoto, and Radu Marinescu. On the complexity of quantum cir- cuit compilation. In Proceedings of the International Symposium on Combinatorial Search , volume 9, pages 138–142, 2018

work page 2018

[5] [4]

Quantum compilation process: A survey

F Javier Cardama, Jorge V´ azquez-P´ erez, Tom´ as F Pena, Juan C Pichel, and Andr´ es G´ omez. Quantum compilation process: A survey. In European Conference on Parallel Processing , pages 100–112. Springer, 2024

work page 2024

[6] [5]

Bench- marking a trapped-ion quantum computer with 30 qubits

Jwo-Sy Chen, Erik Nielsen, Matthew Ebert, Volkan Inlek, Kenneth Wright, Vandiver Chaplin, Andrii Maksymov, Eduardo P´ aez, Amrit Poudel, Peter Maunz, and John Gamble. Bench- marking a trapped-ion quantum computer with 30 qubits. Quantum, 8:1516, November 2024

work page 2024

[7] [6]

Characterizing randomness in parameterized quantum circuits through express- ibility and average entanglement

Guilherme Il´ ario Correr, Ivan Medina, Pedro C Azado, Alexandre Drinko, and Diogo O Soares-Pinto. Characterizing randomness in parameterized quantum circuits through express- ibility and average entanglement. Quantum Science and Technology, 10(1):015008, 2024

work page 2024

[8] [7]

Cross, Lev S

Andrew W. Cross, Lev S. Bishop, Sarah Sheldon, Paul D. Nation, and Jay M. Gambetta. Validating quantum computers using randomized model circuits. Phys. Rev. A , 100:032328, Sep 2019

work page 2019