Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation | Paper Citation Record

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This paper cites Efficient Methods for Mapping Neural Machine Translator on FPGAs,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Efficient Methods for Mapping Neural Machine Translator on FPGAs,

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This paper cites Algorithm-hardware Co-design of Attention Mechanism on FPGA Devices,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Algorithm-hardware Co-design of Attention Mechanism on FPGA Devices,

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This paper cites A Survey of Multilingual Neural Machine Translation,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation A Survey of Multilingual Neural Machine Translation,

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This paper cites Natural Language Processing for Dialects of a Language: A Survey,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Natural Language Processing for Dialects of a Language: A Survey,

Reference 4

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This paper cites SelfSeg: A Self-supervised Sub-word Segmentation Method for Neural Machine Translation,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation SelfSeg: A Self-supervised Sub-word Segmentation Method for Neural Machine Translation,

Reference 5

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This paper cites A Survey: Collaborative Hardware and Software Design in the Era of Large Language Models,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation A Survey: Collaborative Hardware and Software Design in the Era of Large Language Models,

Reference 6

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Observation 454fbce9-e248-4639-b439-44e659869383 · outbound

This paper cites Indic-ST: A Large-Scale Multilingual Corpus for Low-Resource Speech-to-Text Translation,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Indic-ST: A Large-Scale Multilingual Corpus for Low-Resource Speech-to-Text Translation,

Reference 7

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This paper cites OPU: An FPGA- Based Overlay Processor for Convolutional Neural Networks,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation OPU: An FPGA- Based Overlay Processor for Convolutional Neural Networks,

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Observation 59aa01ea-7cbc-4fa8-98e3-47ea01a4ece1 · outbound

This paper cites An Energy-Efficient Reconfigurable LSTM Accelerator for Natural Language Processing,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation An Energy-Efficient Reconfigurable LSTM Accelerator for Natural Language Processing,

Reference 9

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Observation 88f89a3d-ea5d-4b6e-b078-184046adc31d · outbound

This paper cites Towards Building Large Scale Datasets and State-of-the-Art Automatic Speech Translation Systems for 14 Indian Languages.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Towards Building Large Scale Datasets and State-of-the-Art Automatic Speech Translation Systems for 14 Indian Languages

Reference 10

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Observation c829cb4f-f31d-47a1-a187-21f9fb8250a0 · outbound

This paper cites Towards building text-to-speech systems for the next billion users,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Towards building text-to-speech systems for the next billion users,

Reference 11

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Observation e520b929-68ea-41a6-9ffb-bfc9c1f78ce7 · outbound

This paper cites Scaling neural machine translation to 200 languages,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Scaling neural machine translation to 200 languages,

Reference 12

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Observation 7f33d887-5661-452b-bf0a-c4e592514158 · outbound

This paper cites Robust speech recognition via large-scale weak super- vision,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Robust speech recognition via large-scale weak super- vision,

Reference 13

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Observation 458671c0-8283-4425-9219-e8a5bfa07217 · outbound

This paper cites ViTCoD: Vision Transformer Acceleration via Dedicated Algo- rithm and Accelerator Co-Design,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation ViTCoD: Vision Transformer Acceleration via Dedicated Algo- rithm and Accelerator Co-Design,

Reference 14

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This paper cites ViA: A Novel Vision-Transformer Accelerator Based on FPGA,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation ViA: A Novel Vision-Transformer Accelerator Based on FPGA,

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This paper cites EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference,

Reference 16

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Observation c5c2da49-4064-4ff5-8be1-263b50b673ac · outbound

This paper cites Hardware acceleration of fully quantized bert for efficient natural language processing,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Hardware acceleration of fully quantized bert for efficient natural language processing,

Reference 17

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This paper cites AccelTran: A Sparsity-Aware Accelerator for Dy- namic Inference With Transformers,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation AccelTran: A Sparsity-Aware Accelerator for Dy- namic Inference With Transformers,

Reference 18

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This paper cites A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks,

Reference 19

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Observation f87213b5-845f-484f-b626-2a58c5e74d92 · outbound

This paper cites A 3: Accelerating Attention Mechanisms in Neural Networks with Approximation,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation A 3: Accelerating Attention Mechanisms in Neural Networks with Approximation,

Reference 20

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This paper cites Uni-OPU: An FPGA- Based Uniform Accelerator for Convolutional and Transposed Convo- lutional Networks,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Uni-OPU: An FPGA- Based Uniform Accelerator for Convolutional and Transposed Convo- lutional Networks,

Reference 21

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This paper cites HPTA: A High Performance Transformer Acceler- ator Based on FPGA,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation HPTA: A High Performance Transformer Acceler- ator Based on FPGA,

Reference 22

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This paper cites ELSA: hardware-software co-design for efficient, lightweight self-attention mechanism in neural networks,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation ELSA: hardware-software co-design for efficient, lightweight self-attention mechanism in neural networks,

Reference 23

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This paper cites EdgeLLM: A Highly Efficient CPU- FPGA Heterogeneous Edge Accelerator for Large Language Models,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation EdgeLLM: A Highly Efficient CPU- FPGA Heterogeneous Edge Accelerator for Large Language Models,

Reference 24

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This paper cites A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs,

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This paper cites A configurable cloud-scale DNN pro- cessor for real-time AI,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation A configurable cloud-scale DNN pro- cessor for real-time AI,

Reference 26

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This paper cites Occamy: A 432-Core Dual-Chiplet Dual- HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Occamy: A 432-Core Dual-Chiplet Dual- HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET,

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This paper cites Maestro: A 302 GFLOPS/W and 19.8 GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Maestro: A 302 GFLOPS/W and 19.8 GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing,

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Observation c8234a9b-a9c0-4695-89cf-ca0d5a2686eb · outbound

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Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Parallel Accurate Minifloat MACCs for NN Inference on Versal FPGAs,

Reference 29

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Observation eb5ac4ef-83de-4e34-9dde-c13c7b463060 · outbound

This paper cites NVIDIA Blackwell Platform: Advancing Generative AI and Accelerated Computing,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation NVIDIA Blackwell Platform: Advancing Generative AI and Accelerated Computing,

Reference 30

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This paper cites LPRE: Logarithmic Posit-enabled Reconfigurable edge-AI Engine,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation LPRE: Logarithmic Posit-enabled Reconfigurable edge-AI Engine,

Reference 31

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This paper cites AMD XDNA NPU in Ryzen AI Processors,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation AMD XDNA NPU in Ryzen AI Processors,

Reference 32

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This paper cites A Multi-Mode 8k-MAC HW-Utilization- Aware Neural Processing Unit With a Unified Multi-Precision Datapath in 4-nm Flagship Mobile SoC,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation A Multi-Mode 8k-MAC HW-Utilization- Aware Neural Processing Unit With a Unified Multi-Precision Datapath in 4-nm Flagship Mobile SoC,

Reference 33

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Observation 69b367d0-e7e9-41c1-9db3-a4b63259a851 · outbound

This paper cites A Low-Cost Floating-Point FMA Unit Supporting Package Operations for HPC-AI Applications,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation A Low-Cost Floating-Point FMA Unit Supporting Package Operations for HPC-AI Applications,

Reference 34

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Observation 2be3a9ac-5965-45fa-84a9-5195d324705f · outbound

This paper cites RaPiD: AI Accelerator for Ultra-low Precision Training and Inference,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation RaPiD: AI Accelerator for Ultra-low Precision Training and Inference,

Reference 35

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Observation 839f5ad1-41c2-42c9-8441-50e45cf69084 · outbound

This paper cites XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloads.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloads

Reference 36

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This paper cites Exploring Hardware Ac- tivation Function Design: CORDIC Architecture in Diverse Floating Formats,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Exploring Hardware Ac- tivation Function Design: CORDIC Architecture in Diverse Floating Formats,

Reference 37

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This paper cites Retrospective: A CORDIC Based Configurable Activation Function for NN Applications,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Retrospective: A CORDIC Based Configurable Activation Function for NN Applications,

Reference 38

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This paper cites ASTRA: Reconfigurable Training Architecture Design for Nonlinear Softmax and Activation Functions in Transform- ers,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation ASTRA: Reconfigurable Training Architecture Design for Nonlinear Softmax and Activation Functions in Transform- ers,

Reference 39

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Observation 4bde0bd6-565a-4295-a770-24e9e6c280d0 · outbound

This paper cites A Flexible Template for Edge Generative AI With High-Accuracy Accelerated Softmax and GELU,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation A Flexible Template for Edge Generative AI With High-Accuracy Accelerated Softmax and GELU,

Reference 40

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Observation 81e98d69-e1fc-4908-94db-23197207604c · outbound

This paper cites Flex-PE: Flexible and SIMD Multiprecision Processing Element for AI Workloads,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Flex-PE: Flexible and SIMD Multiprecision Processing Element for AI Workloads,

Reference 41

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Observation 7f4a17c9-1611-4771-b449-7d47b05f812a · outbound

This paper cites A Reconfigurable Processing Element for Multiple- Precision Floating/Fixed-Point HPC,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation A Reconfigurable Processing Element for Multiple- Precision Floating/Fixed-Point HPC,

Reference 42

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Observation 1e9f63d0-7500-4a77-b8dd-733adc20fea6 · outbound

This paper cites QuantMAC: Enhancing Hardware Performance in DNNs With Quantize Enabled Multiply-Accumulate Unit,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation QuantMAC: Enhancing Hardware Performance in DNNs With Quantize Enabled Multiply-Accumulate Unit,

Reference 43

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Observation 56cb888d-e39a-412a-a21f-1eea1fc8e80c · outbound

This paper cites ReNPU: A Resource-efficient Multi-Mode Neural Processing Unit with Unified Multi-Precision Datapath for Mobile AI Workloads,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation ReNPU: A Resource-efficient Multi-Mode Neural Processing Unit with Unified Multi-Precision Datapath for Mobile AI Workloads,

Reference 44

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Observation 8f1c05ee-b50e-49e1-8d36-d9e60d83e497 · outbound

This paper cites ReAFM: A Reconfigurable Nonlinear Activation Function Module for Neural Networks,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation ReAFM: A Reconfigurable Nonlinear Activation Function Module for Neural Networks,

Reference 45

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This paper cites QForce- RL: Quantized FPGA-Optimized Reinforcement Learning Compute En- gine,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation QForce- RL: Quantized FPGA-Optimized Reinforcement Learning Compute En- gine,

Reference 46

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This paper cites Flex-SFU: Activation Func- tion Acceleration with Non-Uniform Piecewise Approximation,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation Flex-SFU: Activation Func- tion Acceleration with Non-Uniform Piecewise Approximation,

Reference 47

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This paper cites TEA-S: A Tiny and Efficient Architecture for PLAC-Based Softmax in Transformers,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation TEA-S: A Tiny and Efficient Architecture for PLAC-Based Softmax in Transformers,

Reference 48

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This paper cites ShortcutFusion: From Tensorflow to FPGA-Based Accelerator With a Reuse-Aware Memory Allocation for Shortcut Data,.

Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation ShortcutFusion: From Tensorflow to FPGA-Based Accelerator With a Reuse-Aware Memory Allocation for Shortcut Data,

Reference 49

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