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High-Precision Calibration Workflow Achieves Above $99.9\%$ CZ Gate Fidelity on a Scalable Superconducting Processor

T0 review · 2 major / 1 minor · reviewed 2026-07-03 · grok-4.3

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Pith's one-line read A closed-loop calibration workflow using ELEA and CAFE circuits reaches CZ gate fidelity above 99.9% on an 84-qubit superconducting processor.

desk verdict The paper shows a closed-loop ELEA/CAFE workflow that reaches >99.9% CZ fidelity on an 84-qubit chip with parallel calibration and 9-hour stability, but the fidelity numbers rest on unvalidated error extraction circuits. read the letter →

arxiv 2607.01422 v1 pith:7R3HXV2Y submitted 2026-07-01 quant-ph

Huili Zhang , Meiling Li , Shuang Yang , Yaqing Feng , Yulong Li , Cheng Chen , Pei Liu , Guangming Xue
show 1 more author
Haifeng Yu
This is my paper · ORCID
classification quant-ph
keywords CZgatefidelitysuperconductingprocessorcalibrationworkflowleakageerrorcoherentquantumcomputingtwo-qubitgates
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper develops a closed-loop workflow for calibrating CZ gates on superconducting quantum processors to meet the tight error budgets required for fault-tolerant computation. By applying echoed leakage error amplification and context-aware fidelity estimation circuits, the method suppresses population leakage to non-computational states and coherent errors from parameter deviations. This produces a demonstrated CZ gate fidelity exceeding 99.9% with coherent error held to 0.007% on an 84-qubit device. The same workflow yields a median fidelity of 99.25% across 72 parallel CZ gates and supports fully automated runs that maintain stability over multi-hour periods. The approach therefore supplies a practical route to high-precision two-qubit operations on scalable superconducting hardware.

What carries the argument

The closed-loop workflow that combines echoed leakage error amplification (ELEA) and context-aware fidelity estimation (CAFE) circuits to deliver unbiased, high-precision estimates of leakage and coherent errors during CZ gate tuning.

What would settle it

An independent fidelity measurement on the same 84-qubit processor using a different protocol such as randomized benchmarking that returns a value below 99.9% would falsify the central claim.

Watch

Extended reading notes

Core claim

Utilizing the echoed leakage error amplification (ELEA) and the repurposed context-aware fidelity estimation (CAFE) circuits, we suppress the population leakage to non-computational states, and, for the first time, demonstrate a CZ gate fidelity exceeding 99.9% on an 84-qubit processor, with coherent error suppressed to 0.007%. Meanwhile, we obtain a median fidelity of 99.25% among 72 CZ gates, demonstrating that the workflow can be generalized to the calibration of parallel CZ gates. Finally, we realize automated calibration and observe enhanced stability of the CZ gate throughout 9-hour comparative monitoring experiments.

Load-bearing premise

The ELEA and CAFE circuits supply unbiased high-precision estimates of leakage and coherent errors that translate directly into the reported gate fidelity without measurement artifacts or post-hoc data selection.

Editorial extensions

If this is right

  • The workflow extends to simultaneous calibration of many parallel CZ gates while preserving a median fidelity above 99%.
  • Automated execution of the workflow produces measurable gains in gate stability across at least nine-hour monitoring intervals.
  • Suppression of coherent error to 0.007% leaves more margin within the overall error budget for incoherent errors arising from finite coherence times.
  • The method supplies an efficient calibration path for building larger superconducting processors aimed at fault-tolerant quantum computation.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The same circuits and closed-loop structure could be adapted to calibrate other two-qubit gates such as iSWAP on similar hardware.
  • Repeated application across multiple chips would test whether the 99.9% threshold is reproducible under varying fabrication conditions.
  • Integration with real-time feedback during algorithm execution might further reduce the overhead of error mitigation techniques.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 1 minor

Summary. The manuscript presents a closed-loop calibration workflow for CZ gates on an 84-qubit superconducting processor. It employs echoed leakage error amplification (ELEA) and context-aware fidelity estimation (CAFE) circuits to suppress leakage and coherent errors, claiming CZ gate fidelity exceeding 99.9% (with coherent error at 0.007%) on one gate, a median fidelity of 99.25% across 72 gates, generalization to parallel gates, and improved stability via automated calibration over 9-hour monitoring.

Significance. If the fidelity values are shown to be unbiased and directly measured without post-hoc adjustments, the work would be significant for demonstrating a scalable, automated route to high-fidelity two-qubit gates on large superconducting processors, addressing the tight error budgets needed for fault tolerance.

major comments (2)
  1. [Sections 3 and 4] Sections 3 and 4: The central claim of >99.9% CZ fidelity rests on ELEA and CAFE yielding unbiased estimates of leakage and coherent errors. No side-by-side comparison on the same device against interleaved randomized benchmarking (or other established protocols) is reported; any systematic offset in how CAFE extracts process fidelity or ELEA amplifies leakage would directly affect the headline number without detection by the internal checks shown.
  2. The manuscript provides no explicit description of data exclusion rules, how error bars on fidelity are computed, or whether the reported values derive from direct measurement versus modeling; these details are required to evaluate whether the 99.9% threshold and 0.007% coherent error are robust.
minor comments (1)
  1. [Abstract] The abstract states 'for the first time' without referencing the closest prior experimental benchmarks on similar platforms; a brief comparison would clarify the advance.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the thorough review and valuable feedback on our manuscript. We address each major comment below with point-by-point responses. Where appropriate, we have revised the manuscript to improve clarity and robustness of the presented results.

read point-by-point responses

  1. Referee: [Sections 3 and 4] Sections 3 and 4: The central claim of >99.9% CZ fidelity rests on ELEA and CAFE yielding unbiased estimates of leakage and coherent errors. No side-by-side comparison on the same device against interleaved randomized benchmarking (or other established protocols) is reported; any systematic offset in how CAFE extracts process fidelity or ELEA amplifies leakage would directly affect the headline number without detection by the internal checks shown.

    Authors: We appreciate the referee's emphasis on cross-validation for confirming the absence of systematic bias. ELEA and CAFE were chosen for their ability to amplify specific error channels (leakage and coherent errors) in a controlled manner, with internal consistency checks (e.g., agreement between different sequence lengths and contexts) supporting unbiased extraction. However, we did not conduct a side-by-side comparison against interleaved randomized benchmarking on the same device and gates. In the revised manuscript we have expanded Section 4 with additional theoretical justification for the unbiased nature of the estimators and further internal validation metrics. We agree that an experimental cross-check would strengthen the claims but note that performing it would require substantial additional experimental time not available in the current study. revision: partial

  2. Referee: The manuscript provides no explicit description of data exclusion rules, how error bars on fidelity are computed, or whether the reported values derive from direct measurement versus modeling; these details are required to evaluate whether the 99.9% threshold and 0.007% coherent error are robust.

    Authors: We agree that these methodological details were insufficiently described. In the revised manuscript we have added a new subsection (Section 3.4) that explicitly details: (i) data exclusion rules based on signal-to-noise ratio thresholds and outlier detection via median absolute deviation; (ii) error bar computation via bootstrap resampling over 1000 iterations; and (iii) confirmation that all reported fidelity values are obtained from direct fits to measured data using the CAFE model, with coherent error extracted as a fitted parameter rather than post-hoc adjustment. revision: yes

standing simulated objections not resolved
  • Direct side-by-side experimental comparison of ELEA/CAFE fidelity estimates against interleaved randomized benchmarking on the identical device and gate set is not available in our dataset.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: experimental measurement claim with no derivations or self-referential reductions

full rationale

The paper reports an experimental demonstration of CZ gate fidelity >99.9% on an 84-qubit processor using ELEA and CAFE circuits for error estimation and calibration. No equations, derivations, fitted parameters renamed as predictions, or self-citation chains appear in the provided text. The central claim is a direct measurement result rather than a mathematical reduction to inputs by construction. The workflow is presented as a practical calibration procedure whose outputs (fidelity numbers) are obtained from circuit executions, not defined in terms of themselves. This is the most common honest finding for experimental papers lacking analytic derivations.

Assumptions & free parameters 0 free parameters · 0 assumptions · 0 invented entities

Abstract-only review yields no explicit free parameters, axioms, or invented entities; the claim rests on standard quantum control assumptions whose details are not supplied.

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Cite this review

Pith. "Pith review of High-Precision Calibration Workflow Achieves Above $99.9\%$ CZ Gate Fidelity on a Scalable Superconducting Processor." pith.science (2026). https://pith.science/paper/7R3HXV2Y

@misc{pith2026260701422,
  author       = {Pith},
  title        = {Pith review of: High-Precision Calibration Workflow Achieves Above $99.9\%$ CZ Gate Fidelity on a Scalable Superconducting Processor},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/7R3HXV2Y}},
  note         = {Machine review of arXiv:2607.01422}
}
abstract

High-fidelity universal two-qubit gates are critical for building fault-tolerant quantum computers. In scalable superconducting processors, shortened coherence times introduce more incoherent errors in gate operations. With a constrained error budget, there is reduced tolerance for coherent errors stemming from parameter deviations. In this work, we develop a closed-loop workflow to enhance the CZ gate calibration precision. Utilizing the echoed leakage error amplification (ELEA) and the repurposed context-aware fidelity estimation (CAFE) circuits, we suppress the population leakage to non-computational states, and, for the first time, demonstrate a CZ gate fidelity exceeding $99.9\%$ on an 84-qubit processor, with coherent error suppressed to $0.007\%$. Meanwhile, we obtain a median fidelity of $99.25\%$ among 72 CZ gates, demonstrating that the workflow can be generalized to the calibration of parallel CZ gates. Finally, we realize automated calibration and observe enhanced stability of the CZ gate throughout 9-hour comparative monitoring experiments. Our results, realized on a completely domestic platform, establish an efficient and automated route to quantum computation with superconducting quantum systems.

Figures

Figures reproduced from arXiv: 2607.01422 by the authors.

Figure 1
Figure 1. FIG. 1. The workflow and results for calibrating CZ gates. (a) The experimental results of the effective [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. FIG. 2. Error analysis of CZ gate after calibration. (a) Stan [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. FIG. 3. Error analysis of parallel CZ gates on a scalable superconducting processor. (a) Heatmap of parallel single-qubit (SQ) [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (1 more)
Figure 4
Figure 4. Figure 4: FIG. 4. The error rates of six CZ gates in automated calibra [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]

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