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Static atomic buses replace atom shuttling for long-range gates in fault-tolerant neutral-atom quantum computers, cutting logical error rates by over an order of magnitude.

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2026-07-12 06:56 UTC pith:PZDS6K47

load-bearing objection Concrete static-bus architecture with co-designed high-fidelity CZ pulses and Stim sims; the >10x logical-error edge over shuttling is real under their model but hangs on the optimistic heating constant and omitted laser/field noise they themselves flag. the 2 major comments →

arxiv 2607.02804 v1 pith:PZDS6K47 submitted 2026-07-02 quant-ph

Fault-tolerant quantum computation with static atomic buses

Matteo Bergonzoni , Laura Pecorari , Sam Norrell , Cody Poole , Guido Pupillo , Mark Saffman This is my paper
classification quant-ph PACS 03.67.Lx03.67.Pp32.80.Ee42.50.Dv
keywords neutral-atom quantum computingatomic busesRydberg gatesfault-tolerant quantum computationquantum LDPC codessurface codestransversal gatesoptimal control
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Neutral-atom quantum computers need long-range connections for error correction and logical gates, but moving atoms around adds delay and heating that grow worse as systems get larger. This paper proposes keeping the atoms fixed and using chains of auxiliary mediator atoms—called atomic buses—to create the needed long-range controlled-Z gates. The authors design laser pulses that make these bus-mediated gates fast (a few hundred nanoseconds) and high-fidelity (approaching 99.9 percent) while remaining robust to small motions. Large simulations then show that the static approach yields more than an order-of-magnitude lower logical error rates than shuttling-based designs under realistic noise, with logical gates around 100 microseconds and full error-correction cycles around 1 millisecond for moderate code distances. The result is a modular layout that supports high-rate memory codes, transversal Clifford operations, and magic-state distillation while confining physical atom movement to background reloading.

Core claim

Static atomic buses of mediator atoms can mediate high-fidelity long-range CZ gates that support both long-range stabilizer readout in high-rate LDPC codes and transversal logical gates between neighboring surface-code patches, yielding more than an order-of-magnitude improvement in logical error rates over atom-shuttling architectures and cycle times of about 1 ms for distances d ≲ 12.

What carries the argument

Bus-mediated CZ gates obtained by co-designing time-optimal GRAPE pulses with interaction-flatness (local maxima of the van der Waals potential) and robustness constraints so that mediator atoms begin and end fully disentangled while the end qubits acquire a controlled phase.

Load-bearing premise

The comparison assumes shuttling heating grows as A times distance to the two-thirds power with an optimistic A, while treating idle errors as zero in the static case and omitting laser phase noise and stray fields that affect high-n Rydberg states.

What would settle it

Repeat the Monte-Carlo logical-error simulations of the Bell-pair and La-cross memory circuits after replacing the shuttling-heating model with measured heating rates from a real dual-species array and after injecting laser-phase and electric-field noise into the bus-gate fidelities; if the static advantage disappears below physical error rates of 10^{-3}, the central claim fails.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • Logical transversal gates between surface-code patches become possible in ~100 µs without physical atom transport for distances up to d=11 (and potentially d=25 with higher Rydberg states).
  • High-rate La-cross and bivariate-bicycle LDPC memories can run full syndrome-extraction cycles in ~0.25–1.3 ms using only static bus gates.
  • Atom shuttling can be relegated to background reloading and offline magic-state factories, removing transport latency from the algorithmic clock.
  • A modular layout interleaving high-rate LDPC memories with surface-code processing units becomes practical under present-day Rabi rates and lattice spacings.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same flat-interaction design may transfer to other dual-species platforms once suitable Rydberg pairs are identified, reducing the need for continuous recooling in deep circuits.
  • If measurement heating can also be made negligible, the static architecture could widen its speed advantage over shuttling by another factor of several because recooling overheads would be largely eliminated.
  • Extending the bus to three or more mediators while keeping spontaneous-emission errors below threshold would allow transversal operations between non-adjacent surface-code patches without any physical rearrangement.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 5 minor

Summary. The manuscript introduces a primarily static neutral-atom architecture in which chains of auxiliary mediator atoms (atomic buses) realize long-range CZ gates without qubit transport. Optimal-control (GRAPE) pulses are co-designed for both symmetric (data–ancilla–data) and asymmetric (data–ancilla–ancilla) buses, incorporating interaction-flatness and robustness constraints; the resulting gates reach fidelities approaching 0.999 with durations of a few hundred nanoseconds. The architecture is shown to support transversal logical CZ/CNOT between neighboring surface-code patches (up to d=11, with a path to d=25) and long-range stabilizer readout for La-cross and bivariate-bicycle LDPC codes. Large-scale Stim+BPOSD Monte-Carlo simulations under a hardware-motivated noise model predict more than an order-of-magnitude reduction in logical error rate relative to an atom-shuttling baseline, together with logical-gate times ~100 µs and QEC-cycle times ~1 ms for d ≲ 12. A modular bridging scheme to surface-code compute units and a hybrid quasi-static magic-state factory complete the path to universality.

Significance. If the performance claims hold under realistic noise, the work supplies a concrete, co-designed alternative to shuttling that removes transport latency and heating from the algorithmic clock cycle while retaining the connectivity needed for high-rate LDPC memories and transversal Clifford operations. The combination of microscopic pulse engineering (analytic Rydberg-time scalings, flat-potential selection, ensemble robustness), explicit gate scheduling, and end-to-end logical simulations for multiple code families is a substantial advance over prior conceptual bus proposals. The dual-species layout and restriction of active transport to background reloading and magic-state routing are practically attractive. These elements make the manuscript a valuable blueprint for the next generation of neutral-atom FTQC architectures.

major comments (2)
  1. [Secs. III C, IV B 2; Figs. 4(b), 6; Eq. (19); App. D] The headline claim of “more than an order-of-magnitude improvement in logical error rates” (abstract; Figs. 4(b), 6) rests on a deliberately asymmetric noise model (Secs. III C, IV B 2). Shuttling heating is injected as independent single-qubit depolarizing noise of strength A·d^{2/3} with the optimistic prefactor A=6×10^{-4} (App. D), while static-bus idle errors are set identically to zero and laser phase/frequency noise plus stray-field perturbations of high-n Rydberg states are explicitly excluded from all reported gate infidelities (Sec. III A). The same A and the f(d) scaling of Eq. (19) (and App. E) feed every Monte-Carlo comparison and the cycle-time arithmetic of Secs. III B and IV B 3. A modest reduction in A, or inclusion of the omitted laser/field noise that would raise the bus-gate floor above the ~2–3× nearest-neighbor value used for f(d), would shrink or eliminate the clai
  2. [Sec. IV C 1; Table I] For the bivariate-bicycle [[144,12,12]] code the authors compute a weighted average physical infidelity ⟨1−F⟩=3.4×10^{-3} (Table I) and note that it lies below the pseudo-threshold of Ref. [44], but they explicitly defer a full circuit-level Monte-Carlo simulation “to future work” (Sec. IV C 1). Given that the same architecture is advertised for high-rate LDPC memories, the absence of even a single distance-scaling curve under the bus-gate noise model leaves a gap between the gate-level results and the logical-performance claims made for La-cross codes. Either a limited Stim simulation for the Gross code (or a clear statement that the BB results are only gate-level) is needed to keep the logical claims uniform across code families.
minor comments (5)
  1. [Abstract; Sec. I] The abstract and introduction state “d ≲ 12” / “d < 12” while the body discusses explicit constructions up to d=11 (one- and two-mediator) and a scaling argument to d=25. Align the numerical bounds for consistency.
  2. [Figs. 2, 3] Fig. 2(c.2) and the corresponding panels in Fig. 3 would benefit from an explicit horizontal scale bar (in µm) so that the claimed local-maximum condition can be read off without referring back to the text.
  3. [Sec. III B] In Sec. III B the total transversal-CZ time of 88 µs for d=9 assumes a 1 µs switching overhead and neglects ancilla-reset time; a one-sentence justification that dual-species reset is faster than the switching budget would strengthen the estimate.
  4. [App. E; Eq. (18)] App. E, Eq. (E4) retains the black-body term g2(n+g1)^{-2}; the main-text scaling Eq. (18) drops it. A brief remark that the room-temperature correction is sub-dominant for the n range considered would avoid confusion.
  5. [References] Several self-citations appear as arXiv preprints with future dates (e.g., 2604.25987). Update or replace with published versions where available, or mark clearly as concurrent work.

Circularity Check

0 steps flagged

No significant circularity: gate fidelities from independent GRAPE on the microscopic Hamiltonian; logical-error advantage from Stim Monte-Carlo under an explicit (asymmetric) noise model; self-citations supply methods/background only.

full rationale

The derivation chain is self-contained and non-circular. Time-optimal/robust bus-mediated CZ pulses are obtained by GRAPE minimization of the Bell-state infidelity (or the ensemble-robust cost) on the dual-species Rydberg Hamiltonian (Eqs. 1–3, 7–9); the resulting T and τ_ryd are numerical outputs, not definitions of the target fidelity. Spontaneous-emission and motional infidelities are estimated from those pulses (App. C, F) or from the fitted scalings (Eqs. 15–16, App. E) and then injected as range-dependent depolarizing rates p* = f(d)·p into Stim circuits. Logical error rates (Figs. 4(b), 6) and cycle-time arithmetic (Secs. III B, IV B 3) are therefore Monte-Carlo predictions under a stated noise model (A = 6×10^{-4}, zero static idle, laser/field noise omitted). None of these quantities reduces by construction to a fitted parameter that defines the claim. Self-citations (e.g., [16–18, 44, 75]) supply prior gate-optimization techniques, La-cross/BB constructions, and layout heuristics; they are not uniqueness theorems or load-bearing premises that force the order-of-magnitude advantage. The noise-model asymmetry is a correctness/assumption risk, not circularity. Score 1 reflects only the presence of ordinary self-citations that are not load-bearing.

Axiom & Free-Parameter Ledger

4 free parameters · 5 axioms · 1 invented entities

The central performance claims rest on a small set of hardware parameters chosen to match current or near-term experiments, an optimistic but literature-motivated heating prefactor, and standard CSS/QEC assumptions. No new physical entities are postulated; the atomic bus is an architectural arrangement of known Rydberg interactions.

free parameters (4)
  • shuttling heating prefactor A = 6e-4
    Sets idle error strength p_idle = A · d^{2/3} (or R^{2/3}); chosen as 6×10^{-4} from optimistic experimental estimates and held independent of gate error p.
  • Rabi frequency Ω_max and principal quantum numbers (n_Rb, n_Cs) = Ω_max=2π×2 MHz (baseline); n pairs such as (75,78), (71,69), etc.
    Chosen per geometry (e.g., 2π×2 MHz with n≈70–80 for baseline, higher for improved fidelity) to place interactions near flat regions or strong blockade while remaining experimentally plausible.
  • lattice spacing r_0 = 2.57–3 µm (baseline)
    Tuned (≈2.6–3 µm baseline, down to 1.7 µm for d=25) so that target separations sit at local maxima of the heteronuclear interaction potential.
  • BPOSD scaling factor s = 0.3
    Empirically set to 0.3 to minimize logical error rate below threshold.
axioms (5)
  • standard math CSS stabilizer formalism and transversal CNOT/CZ for surface codes; hypergraph-product construction for La-cross and bivariate bicycle codes.
    Invoked throughout Secs. II–V as the error-correction substrate; standard and externally validated.
  • domain assumption Van der Waals Rydberg interactions B ∝ R^{-6} with species- and n-dependent C6 coefficients computed via ARC; dual-species (Rb/Cs) encoding suppresses crosstalk.
    Sec. II B and App. A; standard atomic physics used to justify flat-potential regions and dual-species mid-circuit measurement.
  • domain assumption Idle errors negligible in static arrays (via lattice spacing or pulse optimization); measurement/reset error = p; single-qubit gates noiseless.
    Noise model of Secs. III C and IV B 2; required for the static-vs-shuttling comparison.
  • domain assumption Minimum-jerk shuttling trajectory yields wall-clock time ∝ d^{1/3} and heating infidelity ∝ d^{2/3}.
    App. D and Sec. III C, citing experimental trajectory work; used to set the shuttling baseline.
  • ad hoc to paper Laser phase/frequency noise and stray electric fields can be neglected relative to spontaneous emission and residual motion for the reported fidelities.
    Explicitly stated as omitted; if false, absolute gate fidelities degrade and the logical advantage shrinks.
invented entities (1)
  • static atomic bus (mediator chain of ancilla atoms) independent evidence
    purpose: Provides long-range CZ without physical transport by sequential Rydberg-mediated interactions along a fixed chain.
    Architectural arrangement of known atoms and interactions; not a new particle or force. Prior theoretical and experimental bus work is cited; the novelty is the FTQC co-design.

pith-pipeline@v1.1.0-grok45 · 44227 in / 3457 out tokens · 33564 ms · 2026-07-12T06:56:18.707011+00:00 · methodology

0 comments
read the original abstract

Efficient quantum error correction and fault-tolerant quantum computing require scalable, high-fidelity long-range connectivity. In neutral-atom quantum computers, this is commonly achieved through atom transport, but shuttling introduces latency and motional heating that worsen with system size. Here, we introduce a neutral-atom architecture based on static atomic buses, in which auxiliary mediator atoms enable long-range entangling operations without qubit transport. The architecture naturally supports long-range stabilizer measurements in high-rate LDPC codes and transversal logical gates between neighboring surface-code patches, enabling a modular framework for efficient logical memories, Clifford computation, and magic-state distillation. To realize these capabilities, we co-design optimal-control protocols for bus-mediated controlled-Z gates that incorporate both microscopic neutral-atom dynamics and architectural constraints. We obtain smooth bus-mediated gates with fidelities approaching 99.9% and durations of a few hundred nanoseconds by combining time-optimal control with interaction-flatness and robustness constraints. Large-scale simulations of quantum error correction and logical entangling operations between neighboring surface-code patches predict more than an order-of-magnitude improvement in logical error rates compared with atom-shuttling architectures under realistic noise. The architecture achieves logical gate times of approximately 100 us and quantum-error-correction cycle times of about 1 ms for code distances d<12. These results establish static atomic buses as a practical alternative to atom shuttling for scalable fault-tolerant neutral-atom quantum computing.

Figures

Figures reproduced from arXiv: 2607.02804 by Cody Poole, Guido Pupillo, Laura Pecorari, Mark Saffman, Matteo Bergonzoni, Sam Norrell.

Figure 1
Figure 1. Figure 1: FIG. 1 [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. One-mediator bus gate for transversal operations between surface codes of distance [PITH_FULL_IMAGE:figures/full_fig_p007_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Transversal CZ gates between surface codes considering Ω [PITH_FULL_IMAGE:figures/full_fig_p009_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. (a) Circuit for the Bell-pair protocol. In orange [PITH_FULL_IMAGE:figures/full_fig_p011_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. CZ gates for long-range stabilizers of the La-cross code. [PITH_FULL_IMAGE:figures/full_fig_p013_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6 [PITH_FULL_IMAGE:figures/full_fig_p015_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. Gate scheduling for [PITH_FULL_IMAGE:figures/full_fig_p016_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. CZ gate for long-range stabilizers of the bivariate bicycle code considering Ω [PITH_FULL_IMAGE:figures/full_fig_p018_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9. Physical qubit layout for the Bivariate Bicycle code. [PITH_FULL_IMAGE:figures/full_fig_p018_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: FIG. 10 [PITH_FULL_IMAGE:figures/full_fig_p023_10.png] view at source ↗

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Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Protocols of coherent motion control for an interaction-driven Rydberg gate

    physics.atom-ph 2026-07 conditional novelty 7.0

    Lattice pinning plus a motion-echo sequence suppresses position-induced errors in interaction-driven Rydberg CZ gates to the 10^-4 level at ~10 ns Rydberg dwell times.

Reference graph

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