Single event effects in the HCCStar ASICs for ITk strip upgrade

Bruce Gallop; Godwin Mayers; Hantao Jing; Jaya John John; Jeff Dandoy; Matt Warren; Mitch Newcomer; Paul Keener; Pedro Leitao; Peter Phillips

REVIEW 3 major objections 8 minor 13 references

Single event effects in the HCCStar ASICs for ITk strip upgrade

T0 review · 3 major / 8 minor · reviewed 2026-08-01 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read Proton-beam tests show the HCCStar chip's triple-modular redundancy cuts single-event upsets to a negligible data-loss rate.

desk verdict Good, honest HCCStar SEE data with an overstated 'conservative upper bound'; the LP loss is more like O(10^-9), but the practical conclusion still holds. read the letter →

arxiv 2607.21116 v1 pith:PG6GSRIV submitted 2026-07-23 physics.ins-det

Shaogang Peng , Jeff Dandoy , Bruce Gallop , Hantao Jing , Jaya John John , Paul Keener , Pedro Leitao , Qiang Li

show 7 more authors

Weiguo Lu Godwin Mayers Mitch Newcomer Peter Phillips Zhixin Tan Matt Warren Yan Zhou

This is my paper · ORCID

classification physics.ins-det

keywords HCCStarsingleeventeffectstriplemodularredundancyprotonirradiationITkstripdetectorHL-LHCradiationtoleranceASIC

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that the triple-modular-redundancy (TMR) protection built into the HCCStar readout chip works: under 20–80 MeV proton irradiation, corrected bit flips in registers occur at about 10^-13 cm^2 per proton per bit, and uncorrected single-event effects in the low-priority readout path are rare enough that the resulting data loss is only about 10^-10 of the normal 400 kHz readout rate. It estimates about 10 corrected bit flips per bit per year in the high-luminosity LHC environment. This matters because the HCCStar is the digital hub of each inner-tracker strip module, and the test provides quantitative evidence that the chip will not lose physics data during the upgrade's lifetime.

What carries the argument

Triple Modular Redundancy (TMR): each critical register bit is stored in three copies and a voting circuit compares them, so a single flipped copy is corrected and logged as a corrected bit flip. The paper measures cross sections for these corrected flips (TMR on) and for actual single-event effects in registers and the LP control path (TMR off), then scales the worst-case LP cross section by an assumed hadron flux of about 10^7 particles per cm^2 per second over 10^7 seconds per year to get expected event rates.

What would settle it

Take a production batch of HCCStar chips, enable TMR, and expose them to a hadron spectrum that mimics the high-luminosity LHC (including higher-energy components). If the average LP-path anomaly rate exceeds the paper's conservative 546 per chip per year—or if most chips behave like the one that showed 13 LP events with TMR on—then the O(10^-10) data-loss fraction and the claim that TMR protects the LP path would fail.

Watch

Extended reading notes

Core claim

The central result is a set of proton-beam cross sections for the HCCStar ASIC. With triplication enabled, the register cross section is about 10^-13 cm^2 per proton per bit, recorded as corrected bit flips; with triplication disabled, the actual single-event-upset cross section rises to about 10^-12 cm^2 per proton per bit. In the low-priority (LP) control path, which relays trigger decisions, the worst measured cross section is 5.46×10^-12 cm^2 per proton, used as a conservative upper limit to estimate 546 LP-related readout anomalies per chip per year—a 10^-10 fraction of the 400 kHz LP readout. The paper also reports that no chip failed after a fluence equivalent to roughly half the expe

Load-bearing premise

The headline rates are computed by multiplying measured 20–80 MeV proton cross sections by an assumed hadron flux of ~10^7 cm^-2 s^-1 for 10^7 s/year in the high-luminosity LHC; if that flux or the beam's representativeness is wrong, the 10^-10 and O(10) numbers scale linearly, and the LP-protection conclusion rests mainly on one of the two chips tested.

Editorial extensions

If this is right

If the central estimate holds, LP-path single-event upsets will discard fewer than one in ten billion readout transactions, so physics data loss from the control path is negligible.
About 10 corrected bit flips per bit per year means the TMR circuits will be busy but manageable; register scrubbing or occasional resets will keep configuration intact.
No chip failures at roughly 24 MRad accumulated dose supports the HCCStar's design margin for the upgrade's radiation budget.
The energy-dependent cross-section rise above 60 MeV suggests that higher-energy hadrons may dominate the real environment, so continued monitoring at operating energies is prudent.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The chip-to-chip variation (one chip showed no LP events with TMR, the other showed as many as without TMR) implies that a larger sample is needed to confirm TMR effectiveness on the control path; a firmware-based parity or timeout check on LP responses could serve as a cheap safety net.
The same scaling method could be applied to the ABCStar's register and data paths, allowing a system-level single-event-effect budget for the whole module rather than per-chip.
A natural testable extension is to expose HCCStars to a mixed hadron field or higher proton energies to see whether the Weibull-like rise continues, which would sharpen the lifetime estimate before final production.

Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

First, the essentials. This paper reports the first proton SEE cross sections for HCCStar v1, including an energy scan from 20 to 80 MeV, and a rate estimate for LP-path data loss. The register TMR result is solid: two chips, CBF cross sections ~10^-13 cm2/bit with TMR on, actual SEEs orders of magnitude higher with TMR off. The paper is honest about chip 152, where TMR didn't reduce LP events (13 vs 15), a chip-to-chip variation they acknowledge. I trust the measurements.

What's not solid is the claim that the LP loss fraction is O(10^-10) with a conservative upper bound. The stress-test note is correct: the LP line is a shared multidrop line to 6-11 ABCStars, so one SET can corrupt the readout transaction for more than one ABC. The paper's 'at most one affected transaction per event' is a lower bound on impact, not an upper bound. With eleven ABCs, 546 anomalies per year becomes ~6000, and the fraction is ~1.5e-9 — still negligible compared to 4e12 transactions, and the practical conclusion survives. But the paper should either fix the wording or bound the multiplicity, otherwise the headline number is not as conservative as advertised.

Two smaller issues. Table 1 has nonzero counts without uncertainties, and Fig. 4 has no error bars; for a paper whose main output is a rate, Poisson error bars should be there. Also, the 'worst-case' ASLP cross section is the 70 MeV point, but Fig. 4 suggests the cross section rises toward 80 MeV; I'd like a sentence confirming that the selected value is indeed the largest across the scan, or use the highest measurement.

Who's this for? People in the ITk strip collaboration, and anyone doing ASIC radiation qualification. It's a useful, citable data point. It deserves a serious referee; the data are real and the soft spots are fixable. I'd send it to review with a request to address the multiplicity issue and add uncertainties.

Referee Report

3 major / 8 minor

Summary. The paper reports proton irradiation tests of HCCStar ASICs for the ATLAS ITk strip upgrade, performed at CSNS with 20–80 MeV protons. It measures corrected bit flips (CBFs) in TMR-protected registers, actual SEEs in registers (ASIR) and in the low-priority (LP) control path (ASLP), and derives cross sections as a function of energy. Using the measured ASLP cross section and an assumed HL-LHC hadron flux of O(10^7) cm^-2 s^-1 for 10^7 s/year, it estimates 546 LP-related readout anomalies per HCC per year, a data-loss fraction O(10^-10) relative to the 400 kHz LP readout, and O(10) corrected bit flips per bit per year. It concludes that TMR effectively reduces SEEs and that LP data loss is negligible.

Significance. The raw data are valuable: direct proton-beam measurements on a production-relevant ASIC, with a large accumulated fluence (~48% of HL-LHC lifetime), and a clear TMR-on/off comparison for registers. The cross sections can feed rate estimates for the ITk upgrade. The rate calculation is transparent and, conditional on the flux assumption, the arithmetic is straightforward. However, the paper's headline quantitative claims rest on two fragile steps: the interpretation of ASLP events as affecting at most one readout transaction, and the generalization from two chips. Neither is fatal to the general conclusion that LP-path SEEs are subdominant, but the specific O(10^-10) bound is not established.

major comments (3)

[§5, Eq. (5.4) and preceding paragraph] The 'at most one affected readout transaction per event' mapping is not a conservative upper bound. Section 3 states that the HCC distributes triggers, readout requests, and control signals to 6–11 ABCStars via shared multidrop lines. An SET on the shared LP line can corrupt the L0tag/BCID matching for all ABCStars on the hybrid. With the maximum 11 ABCStars, 546 anomalies becomes ~6000 per HCC per year, a fraction ~1.5×10^-9, not O(10^-10). The paper should either bound the multiplicity from data (e.g., by correlating anomalies across input channels) or rephrase the result as a lower bound on data-loss impact. This is the central quantitative claim.
[Table 1 and §5: 'From Table 1...' paragraph] The TMR-on ASLP count for chip 152 (13 events) is statistically indistinguishable from the TMR-off count (15 events) under Poisson statistics. Only chip 154 shows TMR suppressing ASLP (0 vs 32). The text acknowledges chip-to-chip variation, but the abstract/conclusion claim that 'TMR effectively reduces SEEs' is not established for the LP path. Table 1 lists no uncertainties for nonzero counts, so the reader cannot judge the significance. Provide Poisson confidence intervals or p-values, and state the chip-152 result as a caveat in the abstract/conclusion if the claim is retained.
[Table 1 and Fig. 4] Cross sections for nonzero event counts are quoted without uncertainties. For example, chip 154 Off ASLP = 32 events gives a ~18% relative Poisson error; chip 152 On ASLP = 13 events gives ~28%. Figure 4 plots cross-section points with no error bars, so the purported energy dependence—especially the 'dramatic rise from 60 MeV onward'—cannot be assessed. Add statistical error bars and, if possible, a fit to a Weibull or similar response curve.

minor comments (8)

[Abstract] Missing space in 'HCCStartoreduce'.
[§3] 'FromtheEoS' missing space.
[Eqs. (5.1), (5.2)] Formatting of '#fluence' and '·' is inconsistent; use a consistent notation.
[Fig. 4] Axis labels for (a) and (b) are garbled in the text; ensure the LaTeX renders correctly.
[§4] Grammar: 'The flux were from...' should be 'The flux ranged from...'.
[§4] The statement that the total fluence is equivalent to 48% of the HL-LHC lifetime is based on dose; please specify the dose-to-fluence conversion used.
[Table 1] Effective monitoring intervals are given as ~2.1 h, but fluences and therefore cross sections differ per chip; clarify how individual fluences are computed if monitoring intervals differ.
[References] Journal names 'Jinst'/'JINST' are inconsistent; follow the journal style.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: measured cross-sections feed standard rate equations; annual rates are extrapolations, not tautological predictions.

full rationale

The derivation chain is linear and empirically grounded: single-event cross-sections are measured in the CSNS proton beam (Table 1, Eq. 5.1, Eq. 5.2), and the yearly rates are obtained by multiplying those measured cross-sections by an assumed HL-LHC hadron flux and annual running time (Eq. 5.3, Eq. 5.4). The O(10) CBFs/bit/year and O(10^-10) LP data-loss fraction are therefore environmental scalings of the beam-test measurements, not quantities defined in terms of the conclusions or fitted to the target output. No parameter is fitted to a subset of data and then reused to 'predict' that same subset. The references to prior work by overlapping authors ([2], [4]) are consistency checks or background, not load-bearing support for the central claim. The 'at most one affected readout transaction per event' assumption in Sec. 5 could be challenged on physics grounds (shared multidrop lines may affect multiple ABCStars), but that is a modeling-conservatism issue, not circular reasoning. The paper is self-contained against its own measurements; the central claims do not reduce to their inputs by construction.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

The central estimates rest on two measured cross-sections (one from chip 154 TMR-off) and assumed HL-LHC flux/time; no new physical entities are introduced. The unvalidated single-transaction mapping and environment equivalence are the main assumptions a reader should question.

free parameters (2)

σ_ASLP worst-case (no TMR) = 5.46×10^-12 cm²/p
Measured on chip 154 with TMR off; inserted into Eq. 5.4 to produce the 546 anomalies/year and O(10^-10) fraction. This is the most load-bearing empirical input.
σ_CBF = ≈1×10^-13 cm²/p/bit
Measured corrected-bit-flip cross-section from TMR-on chips; used in Eq. 5.3 to get O(10) corrected flips/bit/year.

assumptions (4)

domain assumption Measured 20–80 MeV proton cross sections are representative of HL-LHC hadron environment
Eqs. 5.3–5.4 multiply CSNS proton cross-sections by the HL-LHC hadron flux; no spectral weighting or correction is applied.
domain assumption HL-LHC HCCStar exposure is O(10^7) hadrons/cm²/s for 10^7 s/year
Taken from [3], used as the rate normalization in Eq. 5.3; if wrong, all annual rates scale linearly.
ad hoc to paper Each ASLP event corrupts at most one LP readout transaction
Introduced without validation just before Eq. 5.4 to convert event rate to data-loss fraction; a single LP request affecting multiple packets would raise the loss fraction.
standard math Poisson 95% upper limit = 3 events when zero observed
Standard recipe; used for upper limits in Table 1.

how reviews work

0 comments

Cite this review

Pith. "Pith review of Single event effects in the HCCStar ASICs for ITk strip upgrade." pith.science (2026). https://pith.science/paper/PG6GSRIV

@misc{pith2026260721116,
  author       = {Pith},
  title        = {Pith review of: Single event effects in the HCCStar ASICs for ITk strip upgrade},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/PG6GSRIV}},
  note         = {Machine review of arXiv:2607.21116}
}

abstract

Triple Modular Redundancy (TMR) technology has been implemented in the design of the HCCStar to reduce digital state changes and ensure reliable operation. We tested the effectiveness of the protection by placing HCCStar chips in a proton beam. We studied corrected bit flips in registers and actual single event effects in the LCB and LP paths under different proton energies. Our estimate is that the LP data-loss fraction relative to the 400 kHz readout is $O(10^{-10})$ during normal operation and there will be $O(10)$ corrected bit flips per HCCStar bit per year at the HL-LHC.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

13 extracted references

[1]

ATLAS Collaboration,The ATLAS experiment at the CERN large hadron collider,Jinst3(2008) S08003

2008
[2]

R.,et al

Dandoy, J. R.,et al. Irradiation testing of ASICs for the HL-LHC ATLAS ITk Strip Detector,Jinst18 (2023) C02044. – 7 –

2023
[3]

J.,et al

Basso, M. J.,et al. A Starry Byte—proton beam measurements of single event upsets and other radiation effects in ABCStar ASIC Versions 0 and 1 for the ITk strip tracker,Jinst17(2022) P03017

2022
[4]

Peng, Shaogang,et al. Single event effect in ABC ASICs for ITk strip upgrade,Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment(2024) 169531

2024
[5]

PUBDB-2017-09975

ATLAS Collaboration,Technical design report for the ATLAS inner tracker strip detector,No. PUBDB-2017-09975. LHC/ATLAS Experiment, 2017

2017
[6]

R.,et al

Dandoy, J. R.,et al. Testing of the HCC and AMAC functionality and radiation tolerance for the HL-LHC ATLAS ITk Strip Detector,Jinst18(2023) C03017

2023
[7]

Karnik, Tanay and Hazucha, Peter,Characterization of soft errors caused by single event upsets in CMOS processes,IEEE Transactions on Dependable and secure Computing, 2004

2004
[8]

Massengill, and Pascale Gouker,Single event transients in digital CMOS — A review,IEEE Transactions on Nuclear Science, 2013

Ferlet-Cavrois, Veronique, Lloyd W. Massengill, and Pascale Gouker,Single event transients in digital CMOS — A review,IEEE Transactions on Nuclear Science, 2013

2013

Show all 13 references

[9]

J.,et al

Ashmanskas, W. J.,et al. Verification of simulated ASIC functionality and radiation tolerance for the HL-LHC ATLAS ITk Strip Detector,Jinst18(2023) C01029

2023
[10]

Mohammad Dehan Rahman, Md Nazaf Rabbi and Golam Sarowar,Development of DC-DC Converters – A Review,2021 International Conference on Computational Performance Evaluation (ComPE)

2021
[11]

CMS Collaboration,The versatile link, a common project for super-LHC,Jinst4(2009) P12003

2009
[12]

Liu Y, Jing H, Huang L,et al. Physical design of the APEP beam line at CSNS,Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment1042(2022) 167431

2022
[13]

ECSS,Space engineering — Calculation of radiation and its effects and margin policy handbook, ECSS-E-HB-10-12A(2010), ESA Requirements and Standards Division, ESTEC, Noordwijk, The Netherlands. – 8 –

2010

Pith tools

Reviewed August 1, 2026 · model on record in the stance chip above.

[1] [1]

ATLAS Collaboration,The ATLAS experiment at the CERN large hadron collider,Jinst3(2008) S08003

2008

[2] [2]

R.,et al

Dandoy, J. R.,et al. Irradiation testing of ASICs for the HL-LHC ATLAS ITk Strip Detector,Jinst18 (2023) C02044. – 7 –

2023

[3] [3]

J.,et al

Basso, M. J.,et al. A Starry Byte—proton beam measurements of single event upsets and other radiation effects in ABCStar ASIC Versions 0 and 1 for the ITk strip tracker,Jinst17(2022) P03017

2022

[4] [4]

Peng, Shaogang,et al. Single event effect in ABC ASICs for ITk strip upgrade,Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment(2024) 169531

2024

[5] [5]

PUBDB-2017-09975

ATLAS Collaboration,Technical design report for the ATLAS inner tracker strip detector,No. PUBDB-2017-09975. LHC/ATLAS Experiment, 2017

2017

[6] [6]

R.,et al

Dandoy, J. R.,et al. Testing of the HCC and AMAC functionality and radiation tolerance for the HL-LHC ATLAS ITk Strip Detector,Jinst18(2023) C03017

2023

[7] [7]

Karnik, Tanay and Hazucha, Peter,Characterization of soft errors caused by single event upsets in CMOS processes,IEEE Transactions on Dependable and secure Computing, 2004

2004

[8] [8]

Massengill, and Pascale Gouker,Single event transients in digital CMOS — A review,IEEE Transactions on Nuclear Science, 2013

Ferlet-Cavrois, Veronique, Lloyd W. Massengill, and Pascale Gouker,Single event transients in digital CMOS — A review,IEEE Transactions on Nuclear Science, 2013

2013