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Paper Citation Record · LEDGER

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement

As of 11 August 2026, this Paper Citation Record lists 52 of 52 outbound references and 0 inbound Pith citation observations for arXiv:2608.03285.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2608.03285 v1

Coverage vector

measured 52 of 52 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-05T21:50:53.039068Z

measured 52 of 52 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-10T06:31:04.303077+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

52 of 52 outbound references displayed

  • verified exact1
  • verified fuzzy45
  • unresolved6
  • parse uncertain0
  • malformed identifier0
  • metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 8f098d05-18ef-48db-b44c-d7728d73baba · outbound

This paper cites Garnet: A detailed on-chip network model inside a full-system simulator,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Garnet: A detailed on-chip network model inside a full-system simulator,

Reference 1

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Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

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Observation 70add7b0-7eb1-4491-a9d4-4a5f2affd81f · outbound

This paper cites vTrain: A sim- ulation framework for evaluating cost-effective and compute-optimal large language model training,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement vTrain: A sim- ulation framework for evaluating cost-effective and compute-optimal large language model training,

Reference 2

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verified fuzzy
raw_fallback, observed 2026-08-05T21:51:03.167257Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

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Observation 6440994f-a469-4610-90b5-d1ed44de0516 · outbound

This paper cites Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling,

Reference 3

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Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

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Observation 5fd09642-4fc4-44e7-b83f-b8de4d36221a · outbound

This paper cites The gem5 Simulator,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement The gem5 Simulator,

Reference 4

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raw_fallback, observed 2026-08-05T21:51:02.787446Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

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Observation 1d59e3e2-b222-4a3c-a3b4-c576acdea612 · outbound

This paper cites an unresolved cited work.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Unresolved cited work

Reference 5

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unresolved
raw_fallback, observed 2026-08-05T21:51:02.571118Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

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Observation b0dff34c-7724-45a5-b234-1b1c785e2e6f · outbound

This paper cites CHASE: A chiplet architecture simulation and exploration framework with decoupled multi-fidelity optimization,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement CHASE: A chiplet architecture simulation and exploration framework with decoupled multi-fidelity optimization,

Reference 6

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Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:48.249840Z digest=sha256:536752a90368b6847715a015b27b7236ebb3bacb2ad482ef578930f53fa76beb

Observation ca5cd24f-8700-43c8-80b5-5e71bd75b10e · outbound

This paper cites Eval- uating the impacts of reticle requirements in semiconductor wafer fab- rication,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Eval- uating the impacts of reticle requirements in semiconductor wafer fab- rication,

Reference 7

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raw_fallback, observed 2026-08-05T21:51:02.137837Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:48.427993Z digest=sha256:89bcc4ada25c973ce9db3962e9b5cdacbbc3593fc375ca38135eb82a8679dc33

Observation cf43426f-2afe-4cb0-81f6-230b47baa624 · outbound

This paper cites Proteus: Simulating the performance of distributed DNN training,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Proteus: Simulating the performance of distributed DNN training,

Reference 8

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verified fuzzy
raw_fallback, observed 2026-08-05T21:51:01.937892Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:48.619178Z digest=sha256:22a7cdf9687f81f7edf7dd07caaf37de9a9f106a8aeffec03fa1acb09003ae60

Observation cab16560-0356-43bf-b0c5-085ad8c369b5 · outbound

This paper cites Explainable fuzzy neural network with multi-fidelity reinforcement learning for micro- architecture design space exploration,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Explainable fuzzy neural network with multi-fidelity reinforcement learning for micro- architecture design space exploration,

Reference 9

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raw_fallback, observed 2026-08-05T21:51:01.685475Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:48.831206Z digest=sha256:5cd09520d7fa7d316ed3153ab182c535d3eb950d05d17369a631fb47fc2a3cbc

Observation 683b81ec-43e0-4a9e-8074-be4469d818ea · outbound

This paper cites System–technology co-optimization for dense edge archi- tectures using 3-D integration and nonvolatile memory,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement System–technology co-optimization for dense edge archi- tectures using 3-D integration and nonvolatile memory,

Reference 11

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verified fuzzy
raw_fallback, observed 2026-08-05T21:51:01.447324Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:49.288858Z digest=sha256:0823537a1c6b8fbbae250c822f7445a1a652f8af50e6c60c4cd991485caf5a82

Observation b59eed8a-a62c-4ed9-82aa-b3f7395050ca · outbound

This paper cites Monad: Towards cost-effective specialization for chiplet-based spatial accelerators,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Monad: Towards cost-effective specialization for chiplet-based spatial accelerators,

Reference 12

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raw_fallback, observed 2026-08-05T21:51:00.957312Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:49.366340Z digest=sha256:1c033d7384cd947feeb3f87dd9bfa9aeb2d5204a556c82f3706ed36e053312d4

Observation 6a939adb-c54d-4da0-9022-aa7b9209d65b · outbound

This paper cites Wafer- scale computing: Advancements, challenges, and future perspectives,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Wafer- scale computing: Advancements, challenges, and future perspectives,

Reference 13

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Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:49.476511Z digest=sha256:9ccc27ccec3bbec67754407425446eb137ca6ad66dc1bca6539db2e03e3b984b

Observation aa86d2dd-3b67-4837-9c20-1310516442bd · outbound

This paper cites ISPD 2020 physical mapping of neural networks on a wafer-scale deep learning accelerator,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement ISPD 2020 physical mapping of neural networks on a wafer-scale deep learning accelerator,

Reference 14

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raw_fallback, observed 2026-08-05T21:51:00.324526Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:49.635194Z digest=sha256:7801174b082123ddcf13fed4e8b3bda88e65a15162134d3fa1c2962f3b1fc72c

Observation b31159ce-cebe-4e6c-bc0d-ed742b3b7c4b · outbound

This paper cites Union: A unified HW–SW co- design ecosystem in MLIR for evaluating tensor operations on spatial accelerators,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Union: A unified HW–SW co- design ecosystem in MLIR for evaluating tensor operations on spatial accelerators,

Reference 15

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raw_fallback, observed 2026-08-05T21:50:59.928331Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:49.714627Z digest=sha256:a178723bb9e867e8dfffdc6fed0570e1f41178498ed40d3b7da65bfa73e8d306

Observation 01be2d7a-e98d-4891-91a1-e3f8e088afa8 · outbound

This paper cites FireSim: FPGA- accelerated cycle-exact scale-out system simulation in the public cloud,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement FireSim: FPGA- accelerated cycle-exact scale-out system simulation in the public cloud,

Reference 16

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Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:49.792996Z digest=sha256:278b6852f0aab0f6913fd9ae61e0d292b857abaaa584a481876dc2c0e62e422c

Observation 97d73458-1325-4a02-8c56-21dd5e8b5d82 · outbound

This paper cites Impact of RoCE congestion control policies on distributed training of DNNs,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Impact of RoCE congestion control policies on distributed training of DNNs,

Reference 17

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Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:49.905270Z digest=sha256:7ad613ddc86cfd81b3184894c48c8054c08d8d408588ed3c76a7af30494fc2ba

Observation 5f35dbfd-1815-4c3a-9f92-2b8a8d942843 · outbound

This paper cites Optimization by simulated annealing,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Optimization by simulated annealing,

Reference 18

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raw_fallback, observed 2026-08-05T21:50:59.238086Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:49.989750Z digest=sha256:836c147c37f09277663e6324808299a675bbbbecb50c58b3a799e841bc225ab5

Observation 33356d67-7d73-4286-b76b-b991058429e0 · outbound

This paper cites MAESTRO: A data-centric approach to understand reuse, performance, and hardware cost of DNN mappings,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement MAESTRO: A data-centric approach to understand reuse, performance, and hardware cost of DNN mappings,

Reference 19

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raw_fallback, observed 2026-08-05T21:50:59.023836Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:50.137345Z digest=sha256:4974985fa535176a86dc4c786622ac1973d08bf4c3daa6fa70ab9285e4c3f76d

Observation d5cf9c2f-6f64-4ad3-a815-453687cd98a6 · outbound

This paper cites The path to successful wafer-scale integration: The Cerebras story,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement The path to successful wafer-scale integration: The Cerebras story,

Reference 20

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verified fuzzy
raw_fallback, observed 2026-08-05T21:50:58.845082Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:50.236704Z digest=sha256:c4d86af0bc3f12fe0c292fa9acd4a8a3e36b4e4966f4974b2c98411592472aef

Observation f6fed1dc-5e83-4464-95e7-709741faa9ef · outbound

This paper cites ReThermal: Co-design of thermal-aware static and dynamic scheduling for LLM training on liquid-cooled wafer-scale chips,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement ReThermal: Co-design of thermal-aware static and dynamic scheduling for LLM training on liquid-cooled wafer-scale chips,

Reference 21

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raw_fallback, observed 2026-08-05T21:50:58.558143Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:50.318263Z digest=sha256:953220cf9eb3f3c6f9a043851fb42a64dca7462f9750192a64fed3da5c53e1e7

Observation 78260459-7ebb-41d5-a3c5-eaea890612b4 · outbound

This paper cites SPAC: Automating FPGA-based network switches with protocol adaptive customization,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement SPAC: Automating FPGA-based network switches with protocol adaptive customization,

Reference 22

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verified fuzzy
raw_fallback, observed 2026-08-05T21:50:58.213489Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:50.402262Z digest=sha256:3f74e58f7a85d313af3a5b844a169555de7783a61132ab3ac1206a060488088a

Observation 97ee3968-7056-42a7-a0fb-b2d3cf00136e · outbound

This paper cites Swift or exact? boosting efficient microarchitecture DSE via multi-fidelity partial-order prediction,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Swift or exact? boosting efficient microarchitecture DSE via multi-fidelity partial-order prediction,

Reference 23

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verified fuzzy
raw_fallback, observed 2026-08-05T21:50:57.854805Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:50.494667Z digest=sha256:6e3284478a1f6d7f6a8f0899be44a5e861d4cd55aca87a8359848799a4b15490

Observation 09de34c3-3b02-4374-89a3-a2fa05908b11 · outbound

This paper cites Multi-fidelity optimization for high-level syn- thesis directives,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Multi-fidelity optimization for high-level syn- thesis directives,

Reference 24

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raw_fallback, observed 2026-08-05T21:50:57.652653Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:50.590987Z digest=sha256:022c0982ccd129411e88958d0a155b0ebe15e23f1da0eb9d96ef5951d2cc9219

Observation 3a2ef896-b904-4e2e-937b-08b789af9ecb · outbound

This paper cites A 0.297-pj/bit 50.4-gb/s/wire inverter-based short-reach simultaneous bi-directional transceiver for die-to-die interface in 5-nm cmos,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement A 0.297-pj/bit 50.4-gb/s/wire inverter-based short-reach simultaneous bi-directional transceiver for die-to-die interface in 5-nm cmos,

Reference 25

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verified fuzzy
raw_fallback, observed 2026-08-05T21:50:57.494665Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:50.687468Z digest=sha256:ff9b063775a6a237d4ed61a6f0f51b57fb102261059d3af11877e9121ac31d3a

Observation d673d575-8d25-4738-a32e-8074c8b501be · outbound

This paper cites Bunch of wires (bow) phy specification,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Bunch of wires (bow) phy specification,

Reference 26

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verified fuzzy
raw_fallback, observed 2026-08-05T21:50:57.301714Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:50.782076Z digest=sha256:4d8dfca11ce7d4e68212ce93348362e315fa36f2848725ab5b46b023e420586e

Observation f87e67d6-12cd-488d-8df4-8b4a045a9f63 · outbound

This paper cites OpenAI Partners with Cerebras,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement OpenAI Partners with Cerebras,

Reference 27

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raw_fallback, observed 2026-08-05T21:50:57.108650Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:50.859140Z digest=sha256:a7769783e638752ccdb787f10457e61e655d60ac6c9c32c6559a400f59fa8ba5

Observation 54f8ed3a-c41b-4d2b-ba28-35becb0f7261 · outbound

This paper cites MuchiSim: A simulation framework for design exploration of multi-chip manycore systems,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement MuchiSim: A simulation framework for design exploration of multi-chip manycore systems,

Reference 28

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raw_fallback, observed 2026-08-05T21:50:56.923866Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:50.978655Z digest=sha256:091398e75295ce92d4db48db1d37af10d1c8b35de8585acde47c8adacc753d6c

Observation c3cf0831-ffaf-483a-8d0e-79085210e7c7 · outbound

This paper cites Architecting wafer-scale processors—a GPU case study,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Architecting wafer-scale processors—a GPU case study,

Reference 29

Resolution
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raw_fallback, observed 2026-08-05T21:50:56.772430Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:51.062095Z digest=sha256:e2c7c9c7c84e6a412868b2eeb26d04bb6695251687f6c628cf5aa8f03ffbaf0e

Observation 8593e4c4-cab1-490d-ae41-693dc1097380 · outbound

This paper cites Timeloop: A systematic approach to DNN accelerator evaluation,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Timeloop: A systematic approach to DNN accelerator evaluation,

Reference 30

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raw_fallback, observed 2026-08-05T21:50:56.632861Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:51.157011Z digest=sha256:0524cb04c3064aa79286d7dd49a652f2d81f857d2fe455c3619113de062cbdcf

Observation d8200e59-942e-409f-b7d8-e305ea05266e · outbound

This paper cites Application of full-system simulation in exploratory system design and development,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Application of full-system simulation in exploratory system design and development,

Reference 31

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raw_fallback, observed 2026-08-05T21:50:56.443495Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:51.270719Z digest=sha256:b0815c37006a454f3faf496bb79afefca3dea1d2e18c708080f6bc93523546e4

Observation f3ff92e1-c260-4f76-bb86-badadd135f0e · outbound

This paper cites Power delivery for high-performance microprocessors—challenges, solutions, and future trends,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Power delivery for high-performance microprocessors—challenges, solutions, and future trends,

Reference 32

Resolution
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no resolver link, observed 2026-08-05T21:50:51.368782Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-05T21:50:51.368782Z digest=sha256:c2769a3e9b789db09e641f74db1d1c92efd6cd32adb00b3883b264d0861b2a00

Observation 7c299015-aa84-4d62-80f9-825cca3a190f · outbound

This paper cites ASTRA-sim: Enabling SW/HW co-design exploration for distributed DL training platforms,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement ASTRA-sim: Enabling SW/HW co-design exploration for distributed DL training platforms,

Reference 33

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:56.265552Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:51.476985Z digest=sha256:6b331dc7e7ce07d2122209b17e8e7797fc038b1ce2f7f9e300442da8a90d9141

Observation e9d14ea7-c873-4f18-a84d-bb63c266adeb · outbound

This paper cites FRED: A wafer-scale fabric for 3d parallel DNN training,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement FRED: A wafer-scale fabric for 3d parallel DNN training,

Reference 34

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:56.118243Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:51.570482Z digest=sha256:adda8036e7cdd536c0b0f0044e67a4ac210e700c026701eceed09dccb52162ac

Observation 313350e7-a09a-44a9-90f8-d3ccc990f225 · outbound

This paper cites Fast stencil-code computation on a wafer-scale processor,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Fast stencil-code computation on a wafer-scale processor,

Reference 35

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:55.933701Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:51.668058Z digest=sha256:5fbabf066efc8b326b0c9a41c5796304ee3f752b81a466c3a152b5d2257e7ab3

Observation a878697b-bc7c-4fc6-8a41-4e32e95efac9 · outbound

This paper cites Polaris: Multi-Fidelity Design Space Exploration of Deep Learning Accelerators.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Polaris: Multi-Fidelity Design Space Exploration of Deep Learning Accelerators

Reference 36

Resolution
unresolved
no resolver link, observed 2026-08-05T21:50:51.744950Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-05T21:50:51.744950Z digest=sha256:32a3dd6f0dbc872851a62ce7b40e8e64e2bca23e09fa3cede4a5fd2fd8afe89a

Observation 9ee6f5dd-4b02-429f-8607-f1f4f6d9fbf9 · outbound

This paper cites SoW-X: A novel system-on-wafer technology for next generation AI server application,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement SoW-X: A novel system-on-wafer technology for next generation AI server application,

Reference 37

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:55.756945Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:51.817165Z digest=sha256:3ca96b00c3528d236bd6c08f646f084d46f00fe45dc0836017732f869aa62aad

Observation c51f0719-76c8-4dd6-8ed6-d0336d34eeac · outbound

This paper cites MLCommons Chakra: Advancing Performance Benchmarking and Co-design using Standardized Execution Traces.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement MLCommons Chakra: Advancing Performance Benchmarking and Co-design using Standardized Execution Traces

Reference 38

Resolution
unresolved
no resolver link, observed 2026-08-05T21:50:51.872226Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-05T21:50:51.872226Z digest=sha256:53c5dce3618829aeebd9ed72e59eb78db5a5aaf77b9c880dff563ff1084c19b2

Observation 33e6044f-1013-4b5c-9eed-053522ba910d · outbound

This paper cites Correlated multi-objective multi-fidelity optimization for HLS directives design,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Correlated multi-objective multi-fidelity optimization for HLS directives design,

Reference 39

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:55.586770Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:51.950189Z digest=sha256:30ab4213c79392e3f5c88aff8e273c37323ac1ee7a73db14eaad88c712ced82a

Observation 93ad4c97-0ed4-485a-93c1-e00332ee75ef · outbound

This paper cites The microarchitecture of Dojo, Tesla’s exa-scale computer,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement The microarchitecture of Dojo, Tesla’s exa-scale computer,

Reference 40

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:55.436238Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:52.014298Z digest=sha256:f1de0ef9fa3d8c628e479ede5ac83e0d26dccace765150c84849a4a46f50f3ad

Observation d1e0b7cf-c3ad-4626-949f-2cd40689240f · outbound

This paper cites W ATOS: Efficient LLM training strategies and architecture co- exploration for wafer-scale chip,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement W ATOS: Efficient LLM training strategies and architecture co- exploration for wafer-scale chip,

Reference 41

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:55.314939Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:52.159382Z digest=sha256:17bc8e292748d06f6e3ae2622981202a756747bc635c465efbc6f829cc152319

Observation 585e0b83-5b67-49ed-8297-30679cab71b8 · outbound

This paper cites Designing spatial architectures for sparse attention: STAR accelerator via cross-stage tiling,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Designing spatial architectures for sparse attention: STAR accelerator via cross-stage tiling,

Reference 42

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:55.149959Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:52.214295Z digest=sha256:a893d18f77bec4f63d0164ef737cc5d6e605a4ef55c9c57043964ef789735fa3

Observation 07d02595-048d-4f55-b664-2c0699522742 · outbound

This paper cites TEMP: A memory efficient physical-aware tensor partition-mapping framework on wafer-scale chips,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement TEMP: A memory efficient physical-aware tensor partition-mapping framework on wafer-scale chips,

Reference 43

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:54.989057Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:52.283044Z digest=sha256:52b40e571444a97f20e667d49d6e47ab110aac826ead95c9b72a3816965da750

Observation 16409ec5-e606-4352-bdcf-ee00d9ec16e1 · outbound

This paper cites TMAC: Training- targeted mapping and architecture co-exploration for wafer-scale chips,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement TMAC: Training- targeted mapping and architecture co-exploration for wafer-scale chips,

Reference 44

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:54.824572Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:52.349325Z digest=sha256:b4e72618e6417a4b47a595c82845efb685d003db86e0da4832c3b904040a7885

Observation bf743749-c279-458f-b368-5f66ec08a8f6 · outbound

This paper cites MOCAP: Wafer-Scale-Chip-Oriented Memory-Orchestrated Chunked Pipelining Framework for Prefill-Only LLM Inference.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement MOCAP: Wafer-Scale-Chip-Oriented Memory-Orchestrated Chunked Pipelining Framework for Prefill-Only LLM Inference

Reference 45

Resolution
verified exact
local_arxiv, observed 2026-08-05T21:50:53.247085Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:52.423769Z digest=sha256:26bc5aa21eb66b9ab4854e0ef4b904181accf77d935c2d5f1e72451ed2069994

Observation 9a2b1f71-2df9-4cc0-af91-28b58168de6c · outbound

This paper cites Spatial-aware orches- tration of LLM attention on waferscale chips,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Spatial-aware orches- tration of LLM attention on waferscale chips,

Reference 46

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:54.625429Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:52.520159Z digest=sha256:17e780e2ed2c7a45aa3f2c81517f61a08fadefa307246aa072040ee1ae78b1e8

Observation 01f7a6c2-f5f9-4476-840e-efe3510d5512 · outbound

This paper cites ASTRA-sim2.0: Modeling hierarchical networks and disaggregated systems for large-model training at scale,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement ASTRA-sim2.0: Modeling hierarchical networks and disaggregated systems for large-model training at scale,

Reference 47

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:54.438258Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:52.640139Z digest=sha256:d41076b45f0b1c50b09e518dc5410f4839da981e35580c09c345ba25cc2468fa

Observation 2ef57f30-27c1-4a6c-9c4d-3f5dd3297336 · outbound

This paper cites WSC-LLM: Efficient LLM service and architecture co- exploration for wafer-scale chips,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement WSC-LLM: Efficient LLM service and architecture co- exploration for wafer-scale chips,

Reference 48

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:54.249534Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:52.709990Z digest=sha256:39bebc3f86eaa9f109e92853dc8b44f73e088118496e8754d4db3deec7970f44

Observation 541ad73c-cbc0-4613-b013-ff32d6b2e124 · outbound

This paper cites Apollo: Transferable architecture exploration,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Apollo: Transferable architecture exploration,

Reference 49

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:54.062918Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:52.782187Z digest=sha256:720dc38b541b74fa82f89c7796a4e16b62fa5b6812efdd6781de4bdafaa45eac

Observation f6d72dc3-b9b5-48b0-ba44-ef3cca9085dc · outbound

This paper cites an unresolved cited work.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Unresolved cited work

Reference 50

Resolution
unresolved
raw_fallback, observed 2026-08-05T21:50:53.865075Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:52.857097Z digest=sha256:f3001a32f827248740962c424c1da3b498c5950c70bdbb063186f45eb268b0a1

Observation 72fe5cf9-ba96-4a5b-b8fc-0300b536db60 · outbound

This paper cites What is DTCO?: An introduction to design–technology co-optimization,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement What is DTCO?: An introduction to design–technology co-optimization,

Reference 51

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:53.686049Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:52.954850Z digest=sha256:0adb76711cccfe548d87151b1ca267e8d23392b5df460ee0097b4c16adb794f0

Observation 134e4032-e214-47e5-ac3b-dfd18af042f0 · outbound

This paper cites Theseus: Exploring efficient wafer-scale chip design for large language models,.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement Theseus: Exploring efficient wafer-scale chip design for large language models,

Reference 52

Resolution
verified fuzzy
raw_fallback, observed 2026-08-05T21:50:53.490359Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-05T21:50:53.039068Z digest=sha256:0cca4db69e2a89969c5cb4a6deaf18a3bf49795389a48a32c38e0beb62758a52

Observation 8f164d34-edb3-4b25-947b-5ef0eded63d8 · outbound

This paper cites PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training.

Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training

Reference 2024

Resolution
unresolved
no resolver link, observed 2026-08-05T21:50:49.199471Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-05T21:50:49.199471Z digest=sha256:9c8d51c2500c1a2b271047e3353f300d6adaed98d01d2f331c7d8927ddaa0db2

Pith citing papers

No inbound Pith citation observations are available.