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REVIEW 3 major objections 4 minor 51 references

Experimental study of multiple-shot unitary channels discrimination using the IBM Q computers

T0 review · 3 major / 4 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read On the IBM Brisbane processor, the dominant error source in multiple-shot unitary-channel discrimination is multi-qubit entangling-gate error, not circuit depth alone.

desk verdict Useful NISQ benchmarking data undermined by a virtual-RZ depth confound in Example 1 and an unverified label-swapping correction. read the letter →

arxiv 2505.17731 v1 pith:4KABHWXL submitted 2025-05-23 quant-ph

Adam Bílek , Jan Hlisnikovský , Tomáš Bezděk , Ryszard Kukulski , Paulina Lewandowska This is my paper · ORCID
classification quant-ph PACS 03.67.-a
keywords quantumchanneldiscriminationunitarychannelsmultiple-shotparallelandsequentialschemeshybridentanglinggateerrorsnoiseresilienceIBMBrisbaneprocessor
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper asks whether the theoretical promise of multiple-shot quantum channel discrimination survives contact with a real noisy processor. For two unitary channels whose single-copy overlap is too small to distinguish, theory says that parallel, sequential, and rectangular hybrid schemes all become perfect once the number of copies $N$ satisfies $N\theta(V^\dagger U)\geq\pi$, where $\theta$ is the arc length of the spectrum of $V^\dagger U$. Running these circuits on the IBM Brisbane processor, the authors find that neither pure parallel nor pure sequential circuits perform well: parallel circuits drown in entangling-gate errors as the GHZ discriminator widens, while very deep sequential circuits lose to decoherence. The paper's central claim is that hybrid sequentially-paralleled circuits, which minimize entanglement overhead while keeping depth below a threshold, are the most resilient in practice, and that suboptimal majority-voting strategies can beat theoretically optimal circuits in the heaviest noise regime.

What carries the argument

The machine at work is the arc function $\theta(V^\dagger U)$, the length of the smallest arc on the unit circle that contains all eigenvalues of $V^\dagger U$; perfect single-shot discrimination holds iff $\theta\geq\pi$, and $N$ copies give perfect discrimination iff $N\theta\geq\pi$. The paper builds rectangular 'sequentially-paralleled' schemes with width $w$ and depth $d$, $N=wd$, placing $N$ copies of the unknown channel as $d$ layers of $w$ parallel applications. The discriminator is a GHZ-type state produced by a cascade of CNOT or ECR entangling gates, and the measurement is either a shallow 'short' circuit or a deeper XOR-based circuit whose parity bit identifies the channel. The role of this machinery is to make all three schemes theoretically equivalent, all giving $p_{\mathrm{succ}}=1$, so that any observed difference is attributable to hardware noise rather than to the discrimination strategy itself.

What would settle it

Run the same five-plus-qubit discrimination circuits immediately after calibration, randomizing the assignment of the two answer sets across otherwise identical runs and testing two different logical-to-physical mappings. If the 'global bit flip' appears only for one assignment, or follows the logical labels rather than the physical qubits, the systematic-artifact hypothesis is refuted and the corrected probabilities in the figures would need re-baselining.

Watch

Extended reading notes

Core claim

The empirical discovery is that on the IBM Brisbane processor the dominant error source in multiple-shot unitary-channel discrimination is the multi-qubit entangling gate, not circuit depth alone. In the first example (identity versus $R_Z(\pi/N)$), purely sequential circuits stay near $p_{\mathrm{succ}}\approx 0.96$ for $N$ up to 12, while purely parallel circuits drop from near 1 to below 0.5 as width grows, and hybrid schemes degrade as more entangling gates are added. In the second example ($U=\sqrt{X}R_Z(-\pi/2N)\sqrt{X}$ versus $V=\sqrt{X}R_Z(\pi/2N)\sqrt{X}$), sequential schemes win for small $N$, sequentially-paralleled schemes win for $N=64$ and $N=96$, and at $N=1024$ all optimal schemes fail while an explicitly suboptimal scheme with 32 independent sequential chains and majority voting reaches $p_{\mathrm{succ}}=0.56765$. The authors conclude that circuit architectures minimizing entanglement overhead while preserving discrimination power are significantly more resilient to hardware noise, provided their depth does not exceed a threshold.

Load-bearing premise

The load-bearing assumption is that the global bit-flip pattern seen on circuits with five or more qubits is a systematic device artifact, so swapping the expected answer sets is a valid correction; if the flips are state-dependent or sporadic, the corrected success probabilities are not trustworthy.

Editorial extensions

If this is right

  • Circuit designers facing noisy hardware should prefer deeper, narrow circuits over wide, shallow ones, because entangling-gate count rather than depth alone drives the error rate.
  • Rectangular hybrid schemes with intermediate width are the practical operating point for many-copy tasks: wide enough to cut depth, narrow enough to limit entanglement overhead.
  • Theoretically suboptimal strategies, such as independent sequential runs per qubit with majority voting, can outperform every optimal scheme in heavily noisy regimes such as $N=1024$.
  • Hardware-aware compilation, using topology-aware ECR circuits with fixed qubit mapping, can recover roughly 20 percent accuracy on 11-qubit XOR-measurement circuits compared with generic CNOT transpilation.
  • Black-box tasks with many oracle calls, such as quantum phase estimation, should be re-examined under the same depth-versus-entanglement trade-off.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A direct test of the paper's global-bit-flip hypothesis would randomize the logical-to-physical qubit mapping across runs; if the flip follows the logical answer sets rather than the physical qubits, the correction is suspect.
  • The qualitative ranking of schemes on Brisbane may not transfer to devices with different native gate sets or error profiles; the transferable quantity is the per-layer entangling-gate error budget, not the absolute threshold depth.
  • A natural follow-up measures the same three scheme classes across calibration epochs with varying two-qubit gate error rates, to check whether entangling-gate error is the causal driver rather than crosstalk or measurement error.
  • Without a noise model for the observed global bit flips, the 90 percent per-qubit accuracy used to predict the suboptimal strategy's performance should be read as an upper bound, not a calibrated estimate.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper reports experiments on the IBM Quantum processor Brisbane for the multiple-shot discrimination of two qubit unitary channels, comparing purely parallel, purely sequential, and rectangular sequentially-paralleled schemes. Two examples are studied: distinguishing identity from RZ(π/N) with no mid-circuit processing (Example 1), and distinguishing U=√X RZ(−π/2N)√X from V=√X RZ(π/2N)√X using X and √X as processing gates (Example 2). In theory all N=wd schemes achieve perfect discrimination when the angle condition θ(V†U)=π/N holds; the experiments instead show performance degradation that depends on circuit width and depth. The authors also compare CNOT- and ECR-based transpilation strategies, apply M3 measurement-error mitigation, and introduce a post-hoc label-swapping correction for bit-flip anomalies. The central empirical claim is that architectures minimizing entanglement overhead are more resilient to hardware noise as long as circuit depth does not exceed a threshold.

Significance. If the conclusions were fully supported, this would be a useful experimental contribution to NISQ-era benchmarking of quantum channel discrimination, since it tests a theoretically motivated family of discrimination circuits on real hardware and makes the data openly available. The paper has clear strengths: raw and mitigated results are reported together, several transpilation strategies are compared, runs were repeated on different dates, and the data are deposited on GitHub and Zenodo. However, the significance is currently limited by three issues: the virtual-depth confound in Example 1, the unverified and data-dependent bit-flip correction, and the absence of statistical uncertainty estimates for the main quantitative claims. These issues affect the abstract's and conclusion's central statements, so the empirical conclusions should be regarded as preliminary until the concerns are addressed.

major comments (3)
  1. [§5.1, §5.4, Figs. 7 and 8] In Example 1, the 'depth' axis is virtual. On IBM Brisbane, RZ gates are implemented as frame updates, so d successive RZ(π/N) applications on the same qubit compile to a single virtual rotation RZ(dπ/N) with no additional physical duration or gate error. Consequently, both the purely sequential scheme in Fig. 7(a) and the rectangular schemes in Fig. 8 vary only the width of the GHZ preparation and measurement circuits when w·d=N is held fixed; they do not vary the physical depth of the unknown-channel segment. The statement in §5.4 that the results show that the primary source of performance degradation is multi-qubit gate error rather than 'decoherence from circuit depth alone' is therefore not supported by Example 1. The abstract's depth-threshold claim should be based on Example 2, whose unknown channels contain physical √X gates and thus provide a genuine depth axis, or on additional experiments that introduce physical depth without entangling gates.
  2. [§5.5, Fig. 9] The label-swapping correction is applied post hoc whenever the raw success probability drops below 0.5. Because the theoretical prediction is p_succ=1, this procedure guarantees that the corrected value lies above 0.5 and biases the data toward the theoretical expectation. The manuscript itself describes the underlying bit-flip artifact as a hypothesis requiring further investigation, and the cited evidence is not sufficient: the fact that M3 error mitigation has no effect is expected if the error is not a measurement-assignment error, and it does not establish that the flips are global, systematic, or independent of the prepared state. I ask the authors to verify the artifact with dedicated calibration experiments (for example, GHZ states of variable width with known output parity), to state an a priori rule for when swapping is permissible, and to report both raw and corrected values throughout. As written, the corrected probabilities in Fig. 9 and the 90% per-qubit accuracy used in §6.3 rest on an unverified assumption.
  3. [§6.2, §6.3, Figs. 10 and 11] The quantitative comparison of schemes lacks error bars and uncertainty estimates. Each circuit uses 10,000 shots, so binomial sampling error is small but nonzero, and the runs come from a single device over different dates with no explicit treatment of calibration drift or correlated errors. Without confidence intervals or repeated measurements, statements such as 'we received p_succ=0.56765 that is better than any optimal scheme' (§6.3) and the threshold behavior claimed in §6.2 are not yet established. The authors should provide per-point confidence intervals, repeat the key comparisons across device calibrations, and state whether the qualitative trends are stable under those repetitions.
minor comments (4)
  1. [§6.3] The text states 'for k<w−k we guess Φ=ΦU'; the second guess should be Φ=ΦV. Please also clarify which figure supports the 'around 90% accuracy for each qubit' used for the N=1024 suboptimal protocol, since Fig. 10 shows only N=4, 16, and 32.
  2. [§6.1, text after Eq. (16)] The displayed θ expression after Eq. (16) contains the same RZ(−π/(2N)) factor on both sides; it should be V*†U*, with the opposite-sign RZ angle or an explicit dagger, in order to yield θ(RZ(π/N)^d)=π.
  3. [§4.3] The introduction of N=w·d mentions 'where k and l are natural numbers'; this should refer to w and d.
  4. [Abstract and §5.2] There are minor language and typographical issues: 'does not overpass threshold value' should read 'does not exceed threshold value', and 'dimentions' should be 'dimensions'. The figure labels 'Numberofshots' also lack spaces.

Circularity Check

0 steps flagged · score 2.0 of 10

No significant circularity: the central theory-to-experiment comparison is self-contained, with self-citations only in background; the main caveats are experimental-validity issues, not circular derivations.

full rationale

The paper's central comparison is not circular. Section 4.3 fixes the unitary gap by design, θ(V†U)=π/N for N=wd, so the theory predicts p_succ=1 for every width–depth factorization (Eq. 11), and the measured success probabilities in Figs. 7, 8, 10, and 11 are external device data compared against this parameter-free uniform prediction. No fitted parameter is subsequently renamed as a prediction. The post-hoc label-swapping correction in Section 5.5 is explicitly acknowledged by the authors as requiring "further investigation and hypothesis-driven testing"; it is a data-processing validity concern, not a circular step, because the qualitative ranking (sequential high, parallel low, hybrid intermediate) is present in the raw curves before correction. Similarly, the concern that IBM Brisbane implements RZ as a virtual phase update, so the 'depth' axis in Example 1 may not scale physical circuit depth, is an implementation confound rather than a reduction of the output to the input. The self-citations ([4], [17], [26], [37]) appear only as background references for benchmarking and earlier discrimination results, and none is load-bearing for the new derivation or the experimental conclusions. Overall, the claimed derivation chain does not reduce to its own inputs, so the circularity score is low.

Assumptions & free parameters 1 free parameters · 6 assumptions · 1 invented entities

The central results rest on standard channel discrimination theory (diamond norm, arc function) plus two paper-specific postulates: the Example 2 circuit reduction to RZ powers and the existence of a global bit-flip artifact corrected by label swapping. The suboptimal strategy uses an extrapolated per-qubit accuracy rather than a directly measured one. No new particles or forces are introduced.

free parameters (1)
  • per-qubit sequential accuracy for depth d=32 = ~0.90 (extrapolated from Fig. 10)
    Used in Section 6.3 to predict the majority-voting success probability for the N=1024 suboptimal scheme; the value is read from data for other N and not independently measured for this exact depth.
assumptions (6)
  • standard math Diamond norm formula ||Phi_U - Phi_V||_diamond = 2 sqrt(1 - nu^2) with nu = min over numerical range of V-dagger U
    Section 4.1, Eq. (6), taken from refs. [42,43]; sets the theoretical single-shot discrimination probability.
  • standard math Arc function scaling: theta((V^{otimes N})^dagger U^{otimes N}) = N theta(V^dagger U) for N theta(V^dagger U) < 2 pi
    Section 4.2, from ref. [32]; used to derive the condition N >= pi/theta for perfect multiple-shot discrimination.
  • standard math With mid-processing X_i = (V^dagger)^{otimes w}, the hybrid scheme achieves theta = pi and perfect discrimination for all w,d with wd=N
    Section 4.3, Eq. (11), from ref. [32]; guarantees all tested schemes have p_succ=1 in the noiseless limit.
  • domain assumption In Example 2, the processed circuit reduces to (RZ(+-pi/(2N))^d)^{otimes w}
    Section 6.1, Eq. (16), stated as 'easy to check'; the paper does not prove the gate identities, and the entire Example 2 relies on this reduction.
  • ad hoc to paper The observed bit-flip patterns for 5+ qubit circuits are a systematic hardware/software artifact that can be corrected by swapping the expected answer sets
    Section 5.5 and Fig. 9; this assumption is introduced only to rescue data points with p<0.5, with no root-cause verification.
  • domain assumption Two-qubit entangling gate errors dominate over decoherence from circuit depth in the tested regime
    Section 5.4; the conclusion that entanglement overhead is the primary error source is inferred from comparing circuits that differ in both width and depth, without a noise model.
invented entities (1)
  • Systematic global bit-flip artifact on IBM Brisbane for 5+ qubit circuits
    purpose: Explains and corrects success probabilities below 0.5 in the parallel and hybrid discrimination experiments
    Postulated in Section 5.5; no calibration data or device-level evidence is provided, and M3 mitigation gave no signal. The correction based on this entity is used to produce the reported accuracies in Fig. 9 and to support the per-qubit accuracy extrapolation.

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Cite this review

Pith. "Pith review of Experimental study of multiple-shot unitary channels discrimination using the IBM Q computers." pith.science (2026). https://pith.science/paper/4KABHWXL

@misc{pith2026250517731,
  author       = {Pith},
  title        = {Pith review of: Experimental study of multiple-shot unitary channels discrimination using the IBM Q computers},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/4KABHWXL}},
  note         = {Machine review of arXiv:2505.17731}
}
read the original abstract

Tasks involving black boxes appear frequently in quantum computer science. An example that has been deeply studied is quantum channel discrimination. In this work, we study the discrimination between two quantum unitary channels in the multiple-shot scenario. We challenge the theoretical results concerning the probability of correct discrimination with the results collected from experiments performed on the IBM Quantum processor Brisbane. Our analysis shows that neither too deep quantum circuits nor circuits that create too much entanglement are suitable for the discrimination task. We conclude that circuit architectures which minimize entanglement overhead while preserving discrimination power are significantly more resilient to hardware noise if their depth does not overpass threshold value.

Figures

Figures reproduced from arXiv: 2505.17731 by the authors.

Figure 1
Figure 1. CNOT im￾plementation of the dis￾criminator. √ X Ecr 1 √ X Ecr 1 0 √ X Ecr 0 0 X √ X 1 Ecr 0 X √ X 1 Ecr 0 √ X 1 [PITH_FULL_IMAGE:figures/full_fig_p008_1.png] view at source ↗
Figure 3
Figure 3. CNOT implementation of the short measurement. • • • • H • • • • • • [PITH_FULL_IMAGE:figures/full_fig_p009_3.png] view at source ↗
Figure 5
Figure 5. ECR implementation of the short measurement. circuit, but it has to be done specifically for every number of qubits. The second possibility is to use swap gates. This enables relatively easy mapping of the circuits, but it enlarges the depth of the circuits. 5.3. Comparative analysis of transpilation. To evaluate the efficacy of different quan￾tum circuit transpilation approaches, particularly concerning the choice … view at source ↗
Figures from the paper (6 more)
Figure 6
Figure 6. Figure 6: ECR implementation of the XOR measurement. XOR-based measurement scheme, while varying the transpilation method. In all these cases, a pure parallel discrimination scheme was employed. 5.3.1. 6-qubit system evaluation. For the 6-qubit configuration, four distinct trans…
Figure 7
Figure 7. Figure 7: Probability of successful discrimination between the identity operation and the RZ(π/N) gate, where N is number of copies of unknown unitary. The dashed red line corresponds to the XOR-based measurement strategy, while the solid blue line represents the short measureme…
Figure 8
Figure 8. Figure 8: Probability of successful discrimination between the identity operation and the RZ(π/N) gate, where N is number of copies of unknown unitary as a function of the width of hybrid rectangular scheme. The dashed red line corresponds to the XOR-based measurement strategy, …
Figure 9
Figure 9. Figure 9: Probability of successful discrimination between the identity gate and the RZ(π/N) gate, where N is number of copies of unknown uni￾tary as a function of the number of channel uses in purely parallel scheme, after applying post-processing correction. The dashed red lin…
Figure 10
Figure 10. Figure 10: Probability of successful discrimination between the unitary operator U = √ XRZ( −π 2N ) √ X and V = √ XRZ( π 2N ) √ X, where N is num￾ber of copies of unknown unitary as a function of the width of hybrid rect￾angular scheme using the short measurement. The blue line …
Figure 11
Figure 11. Figure 11: Probability of successful discrimination between the unitary operator U = √ XRZ( −π 2N ) √ X and V = √ XRZ( π 2N ) √ X, where N is num￾ber of copies of unknown unitary as a function of the width of hybrid rect￾angular scheme using the short measurement. The blue line …

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