Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures | Paper Citation Record

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This paper cites an unresolved cited work.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Unresolved cited work

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Demystifying the Nvidia Ampere Architecture through Microbenchmarking and Instruction-level Analysis

Reference 2

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This paper cites AMD64 architecture programmer’s manual,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures AMD64 architecture programmer’s manual,

Reference 3

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Mosaic: A GPU memory manager with application-transparent support for multiple page sizes,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures MASK: Redesigning the GPU memory hierarchy to support multi-application concurrency,

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This paper cites Analyzing CUDA workloads using a detailed GPU simulator,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Analyzing CUDA workloads using a detailed GPU simulator,

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This paper cites Translation caching: Skip, don’t walk (the page table),.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Translation caching: Skip, don’t walk (the page table),

Reference 7

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures SpecTLB: A mechanism for speculative address translation,

Reference 8

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This paper cites Griffin: Hardware-software support for efficient page migration in multi-GPU systems,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Griffin: Hardware-software support for efficient page migration in multi-GPU systems,

Reference 9

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This paper cites Valkyrie: Leveraging inter- TLB locality to enhance GPU performance,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Valkyrie: Leveraging inter- TLB locality to enhance GPU performance,

Reference 10

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This paper cites A study of replacement algorithms for a virtual-storage computer,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures A study of replacement algorithms for a virtual-storage computer,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Large-reach memory management unit caches,

Reference 12

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This paper cites Translation-triggered prefetching,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Translation-triggered prefetching,

Reference 13

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Shared last-level TLBs for chip multiprocessors,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Inter-core cooperative TLB prefetchers for chip multiprocessors,

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This paper cites Space/time trade-offs in hash coding with allowable errors,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Space/time trade-offs in hash coding with allowable errors,

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This paper cites A quantitative study of irregular programs on GPUs,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures A quantitative study of irregular programs on GPUs,

Reference 17

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Pannotia: Understanding irregular GPGPU graph applications,

Reference 18

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This paper cites Rodinia: A benchmark suite for heterogeneous computing,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Rodinia: A benchmark suite for heterogeneous computing,

Reference 19

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This paper cites A performance study of general-purpose applications on graphics pro- cessors using CUDA,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures A performance study of general-purpose applications on graphics pro- cessors using CUDA,

Reference 20

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This paper cites Heliostat: Harnessing ray tracing accelerators for page table walks,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Heliostat: Harnessing ray tracing accelerators for page table walks,

Reference 21

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This paper cites Barre chord: Efficient virtual memory translation for multi-chip-module GPUs,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Barre chord: Efficient virtual memory translation for multi-chip-module GPUs,

Reference 22

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This paper cites Interplay between hardware prefetcher and page eviction policy in CPU-GPU unified virtual memory,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Interplay between hardware prefetcher and page eviction policy in CPU-GPU unified virtual memory,

Reference 23

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Parallel computing experiences with CUDA,

Reference 24

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This paper cites Auto-tuning a high-level language targeted to GPU codes,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Auto-tuning a high-level language targeted to GPU codes,

Reference 25

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This paper cites Dynamically linked MSHRs for adaptive miss handling in GPUs,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Dynamically linked MSHRs for adaptive miss handling in GPUs,

Reference 26

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures R2D2: Removing redundancy utilizing linearity of address generation in GPUs,

Reference 27

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This paper cites LATPC: Locality-aware TLB prefetching and MSHR compression,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures LATPC: Locality-aware TLB prefetching and MSHR compression,

Reference 28

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Evaluating associativity in CPU caches,

Reference 29

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Intel® 64 and IA-32 architectures software devel- oper’s manual,

Reference 30

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Back to the future: Leveraging Belady’s algorithm for improved cache replacement,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures High performance cache replacement using re-reference interval prediction (RRIP),

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Going the distance for TLB prefetching: An application-driven study,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Redundant memory mappings for fast access to large memories,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Accel-Sim: An extensible simulation framework for validated GPU modeling,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Sampling dead block prediction for last-level caches,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Batch-aware unified memory management in GPUs for irregular workloads,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures CTA-aware prefetching and scheduling for GPU,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures SnakeByte: A TLB design with adaptive and recursive page merging in GPUs,

Reference 40

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures STAR: Sub-entry sharing-aware TLB for multi-instance GPU,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Trans-FW: Short circuiting page table walk in multi-GPU systems via remote forwarding,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Improving address translation in multi-GPUs via sharing and spilling aware TLB design,

Reference 43

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Virtual address translation via learned page table indexes,

Reference 44

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Prefetched address translation,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Evaluation techniques for storage hierarchies,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Dead page and dead block predictors: Cleaning TLBs and caches together,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Snake: A variable-length chain-based prefetching for GPUs,

Reference 48

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures NVIDIA GeForce RTX 3070 family,

Reference 49

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures NVIDIA ampere GA102 GPU architecture whitepaper,

Reference 50

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Systems and methods for coalescing memory accesses of parallel threads,

Reference 51

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Hybrid TLB coalesc- ing: Improving TLB translation coverage under diverse fragmented memory allocations,

Reference 52

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures A case for speculative address translation with rapid validation for GPUs,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Increasing TLB reach by exploiting clustering in page translations,

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures CoLT: Coalesced large-reach TLBs,

Reference 55

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Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Architectural support for address translation on GPUs: Designing memory management units for CPU/GPUs with unified address spaces,

Reference 56

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Observation b01f8f90-92a7-4bef-a7c2-01b9dd0dd75d · outbound

This paper cites Supporting x86-64 address translation for 100s of GPU lanes,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Supporting x86-64 address translation for 100s of GPU lanes,

Reference 58

Resolution: unresolved; no resolver link, observed 2026-06-28T18:32:33.189475Z

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Observation 7d46a917-5320-4e10-ae28-418408b6f5ac · outbound

This paper cites A case for MLP-aware cache replacement,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures A case for MLP-aware cache replacement,

Reference 59

Resolution: unresolved; no resolver link, observed 2026-06-28T18:32:33.189475Z

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Observation 48b96bc3-8bd4-4470-9596-173e8f888a23 · outbound

This paper cites The evicted- address filter: A unified mechanism to address both cache pollution and thrashing,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures The evicted- address filter: A unified mechanism to address both cache pollution and thrashing,

Reference 60

Resolution: unresolved; no resolver link, observed 2026-06-28T18:32:33.189475Z

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Observation f1d03634-5091-4bf5-a61d-8bfd7ce09144 · outbound

This paper cites Scheduling page table walks for irregular GPU applications,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Scheduling page table walks for irregular GPU applications,

Reference 61

Resolution: unresolved; no resolver link, observed 2026-06-28T18:32:33.189475Z

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Observation e4f9d10f-2a99-46f8-aa04-9e1e8b288494 · outbound

This paper cites Elastic cuckoo page tables: Rethinking virtual memory translation for parallelism,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Elastic cuckoo page tables: Rethinking virtual memory translation for parallelism,

Reference 62

Resolution: unresolved; no resolver link, observed 2026-06-28T18:32:33.189475Z

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Observation b91b11ee-47fd-4537-9424-1f174526652c · outbound

This paper cites Parboil: A revised benchmark suite for scientific and commercial throughput computing,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Parboil: A revised benchmark suite for scientific and commercial throughput computing,

Reference 63

Resolution: unresolved; no resolver link, observed 2026-06-28T18:32:33.189475Z

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Observation 87cec520-e60a-4952-a2ba-361b6d09cfb6 · outbound

This paper cites OASIS: Object-aware page management for multi-GPU systems,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures OASIS: Object-aware page management for multi-GPU systems,

Reference 64

Resolution: unresolved; no resolver link, observed 2026-06-28T18:32:33.189475Z

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Observation 8425bb34-7113-4947-a241-da57030258a8 · outbound

This paper cites Translation ranger: Operating system support for contiguity-aware TLBs,.

Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures Translation ranger: Operating system support for contiguity-aware TLBs,

Reference 65

Resolution: unresolved; no resolver link, observed 2026-06-28T18:32:33.189475Z

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