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REVIEW 3 major objections 4 minor 57 references

ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuits

T0 review · 3 major / 4 minor · reviewed 2026-08-01 · deepseek-v4-flash

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Pith's one-line read ParasGB is the first open benchmark that supplies graph-learning models with large-scale, physically grounded parasitic RC labels for analog and SRAM circuits.

desk verdict A genuinely useful RC benchmark for AMS parasitic prediction, but the analog held-out split looks contaminated by an apparent duplicate (IDs 5 and 7) and needs correction before the cross-design claims can be trusted. read the letter →

arxiv 2607.23225 v1 pith:B2LJPKQL submitted 2026-07-25 cs.LG

Jiajun Zou , Jiawei Liu , Ao Liu , Junnong Tian , Yibin Zhang , Chengjie Liu , Yuxi Wang , Shan Shen
show 3 more authors
Wenhua Gu Jun Yang Wenjian Yu
This is my paper
classification cs.LG
keywords parasiticestimationcircuitgraphsbenchmarksuitegraphneuralnetworksanalog/mixed-signalSRAMeffectiveresistancecouplingcapacitance
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

ParasGB is a benchmark suite that supplies what parasitic-aware circuit learning has lacked: large-scale, physically grounded circuit graphs with ground-truth parasitic labels extracted by commercial EDA tools from real, tape-out-proven analog and SRAM designs. The paper's central claim is that this fills the gap left by earlier schematic-level analog benchmarks, which provide topology but no RC supervision. It defines node-level ground capacitance and edge-level effective resistance and coupling capacitance as learning tasks, in both regression and classification forms, with a unified evaluation protocol. The paper benchmarks common GNNs and circuit-specific models, and reports that parasitic labels are extremely imbalanced and long-tailed, making accurate prediction—especially of effective resistance on unseen analog topologies—genuinely hard. A sympathetic reader would care because a reliable public benchmark is the precondition for measurable progress on early-stage parasitic estimation, which in turn could cut costly layout iterations in deep-submicron AMS design.

What carries the argument

The central object is the benchmark suite itself: a conversion pipeline that reduces post-layout RC networks to lumped heterogeneous circuit graphs—device/net/pin nodes with topology edges as input, and ground capacitance (node), effective resistance (edge), and coupling capacitance (edge) as prediction targets. Effective resistance is computed efficiently by building the node admittance matrix and taking the inverse of its Cholesky factor, so port-to-port resistances can be queried without expensive path searches. A unified evaluation module standardizes metrics across models, making results comparable across methods.

What would settle it

Compare the released netlists or graph files for analog circuit IDs 5 and 7; if they are identical (same node and edge counts, same Cg and Reff statistics, same layout files), the held-out test set is not truly unseen, and that would settle whether the claimed cross-design generalization for analog circuits holds.

Watch

Extended reading notes

Core claim

On its own terms, the paper establishes ParasGB as the first open-source benchmark for pre-layout parasitic parameter prediction on circuit graphs. The dataset is built from commercial EDA extraction on silicon-proven designs, converted into heterogeneous graphs with device, net, and pin nodes. The labels are lumped ground capacitance on net nodes, effective resistance on pin-to-pin edges computed via a Cholesky-factor-based method, and coupling capacitance on net-pair edges for SRAM. The benchmark provides a standardized API and train/validation/test splits, including held-out analog circuits and much larger unseen SRAM arrays. Across eight baseline models, the paper shows that current GNNs

Load-bearing premise

The 20 analog circuits in Table 2 are 20 distinct physical designs, so the held-out test IDs 5, 14, and 20 were never seen during training; if two listed circuits are actually the same design, the claimed cross-design generalization results for analog tasks are invalid.

Editorial extensions

If this is right

  • GNN research on parasitic estimation can move from private, inconsistent datasets to a single public testbed where any proposed model can be compared on identical splits and metrics.
  • The held-out analog circuits and much larger unseen SRAM arrays make cross-design generalization a measurable property, not an assumption.
  • The documented extreme label imbalance and long-tail distributions imply that imbalance-aware losses and robust regression methods are core requirements for useful parasitic prediction, not optional extras.
  • The SRAM subset, with graphs up to tens of millions of nodes, gives graph learning researchers a concrete scalability challenge at industrial scale.
  • If pre-layout GNN predictions become reliable on this benchmark, front-end designers could act on estimated parasitics for sizing, buffering, and floorplanning decisions before layout, shortening design convergence.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial inference: the benchmark's fixed five-bin classification boundaries give a consistent physical scale across designs, so the dataset could also serve as a testbed for ordinal regression and label-noise studies, not just standard classification.
  • Editorial inference: because the lumped-model labels abstract away detailed routing geometry, a natural follow-up is to quantify the gap between GNN predictions trained on ParasGB and full post-layout extraction; that gap would reveal the ceiling imposed by the lumped approximation itself.
  • Editorial inference: the cross-scale SRAM split (train on small digital/memory blocks, test on whole arrays) invites a study of how far inductive graph models can extrapolate in graph size and topology—a question that extends beyond EDA to graph learning generally.
  • Editorial inference: the authors stop at benchmarking; one could use ParasGB to train a single multi-task model that predicts all three parasitic targets jointly, testing whether shared representations across node- and edge-level tasks improve accuracy on the hard effective-resistance task.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper presents ParasGB, a benchmark suite for pre-layout parasitic prediction on analog/mixed-signal and SRAM circuit graphs. It provides node-level ground-capacitance, edge-level effective-resistance, and edge-level coupling-capacitance labels extracted with commercial EDA tools from tape-out-proven designs, and defines unified regression and classification tasks. The paper benchmarks several general-purpose GNNs and two circuit-specific baselines on these tasks, reporting mixed results that highlight label imbalance and cross-design generalization challenges.

Significance. If the data-integrity issues are resolved, ParasGB would be a valuable contribution: it is the first open-source benchmark suite of its kind with post-layout RC labels, it is built from industrial designs using commercial extraction tools, and it ships a public repository, an OGB-style API, and unusually detailed preprocessing and normalization equations. The SRAM subset is particularly notable for its scale (up to 11.7M nodes) and dense coupling-capacitance labels. The benchmark also exposes realistic challenges (long-tail distributions, structural heterogeneity) that are likely to be useful to the graph-learning and EDA communities. However, the analog subset contains an apparent duplicate design and the split description omits three listed circuits, so the benchmark's core claim of 20 distinct analog designs and a clean cross-design evaluation is not currently supported as written.

major comments (3)
  1. [Table 2 / Appendix A.2] IDs 5 and 7 in Table 2 are identical in every reported statistic (nodes, edges, C_g, R_eff, citation [19]), and Appendix A.2 gives them the same verbatim description. This strongly indicates the same physical design is listed twice. Since ID 5 is held out for cross-design evaluation and ID 7 is not listed in the training set of Appendix D.1, the duplicate does not necessarily contaminate training under the stated split, but it invalidates the claim of 20 distinct analog circuits and makes the held-out evaluation ambiguous. The authors must either confirm that IDs 5 and 7 are distinct and explain the identical entries, or deduplicate the dataset and re-run the affected experiments.
  2. [Appendix D.1 / Tables 8, 9, 13, 14] The analog split is not well-defined as written. Appendix D.1 states that circuits 1–4, 6, 8–12, and 15–18 are used for training/validation while 5, 14, and 20 are held out, but this accounts for only 17 of the 20 circuits listed in Table 2. IDs 7, 13, and 19 are omitted from the split and from all reported experiments. If the intended training range included ID 7, then the held-out ID 5 is a duplicate of a training circuit and the analog cross-design results are contaminated. If IDs 7, 13, and 19 are intentionally unused, the manuscript must say so and remove them from the claimed dataset inventory. As written, the evaluation protocol is not reproducible from the information given.
  3. [Section 3.1 / Table 2] The manuscript repeatedly emphasizes '20 analog circuits' and uses this count to support the benchmark's breadth. The duplicate ID 5/7 and the absence of IDs 13 and 19 from experiments mean the actual number of distinct, used analog designs is at most 17. All statistics in Table 2, the histograms in Appendix A.3, and the scale groupings in Table 4 should be reconciled with the split description. This is load-bearing for the central claim of a comprehensive analog benchmark.
minor comments (4)
  1. [References] References [19] and [20] are the same paper: K. N. Leung and P. K. T. Mok, 'A CMOS voltage reference based on weighted Delta-V_GS for CMOS low-dropout linear regulators,' JSSC 38(1), 2003. They should be merged and cited consistently.
  2. [Appendix D.1] The set notation 'circuits 1–4, 6, 8–12, and 15–18' is ambiguous regarding whether ID 7 is included. Please use an explicit enumeration or set-builder notation.
  3. [Appendix C.2] The SRAM capacitance validity window in Eq. (3), 1e-21 < C < 1e-15, is introduced without physical justification. The replacement of invalid ground-capacitance labels with 1e-30 in Eq. (5) also deserves a comment on how such measurements arise and whether they could bias the normalized distribution.
  4. [Table 3] The row label 'sram' appears to be an abbreviation of 'ssram' used elsewhere (e.g., Table 6 and Appendix A.2). Please use consistent dataset names.

Circularity Check

0 steps flagged · score 1.0 of 10

No meaningful circularity; the benchmark construction is self-contained, and the only self-citations are not load-bearing.

full rationale

ParasGB is a dataset/benchmark paper, not a derivation of a fitted theory. Its central claim is the release of an open, physically grounded RC benchmark and a standardized evaluation protocol. The label normalization equations (Appendix C, Eqs. 12–14) are computed from the training split and then fixed for validation/test, which is standard supervised practice and is explicitly stated; no test label is used to define the normalization. The parasitic targets come from commercial extraction tools (Calibre xRC, StarRC) and a published matrix-based effective-resistance algorithm, not from the GNN predictions being benchmarked. The GNN experiments are evaluations, so a model performing well does not make the benchmark's construction circular. Self-citations appear in the CircuitGPS/CircuitGCL baselines and in the Appendix A.2 preprocessing note ('following the preprocessing pipeline described in [37]', where [37] shares authors), but these are not load-bearing for the 'first open-source benchmark' claim, which rests on the dataset itself and the comparison with CircuitNet, CktGNN, AMSNet, and AnalogGenie. The notable internal inconsistency is a data-integrity concern, not circularity: Table 2 lists IDs 5 and 7 with identical node/edge counts, identical Cg and Reff statistics, and the same reference [19], with identical descriptive text in Appendix A.2; Appendix D.1 says training uses IDs 1–4, 6, 8–12, and 15–18, held out are 5, 14, 20, leaving IDs 7, 13, and 19 unaccounted for. This could invalidate the clean cross-design evaluation if, say, ID 7 were actually in the training set or if the held-out ID 5 is duplicated elsewhere, but it does not reduce any prediction to its input by construction. Therefore the circularity score is minimal.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The central contribution is a dataset and benchmark, so the ledger contains no free parameters of a scientific derivation. The listed items are the normalization/filtering constants chosen by hand and the domain assumptions required to treat commercial extraction + lumped reduction + schematic features as a valid supervision signal. The duplicate ID 5/7 issue is not an axiom but a data-integrity flaw and is captured in red_flags.

free parameters (4)
  • SRAM capacitance validity bounds = 10^-21 < C < 10^-15 F
    Chosen by hand in Appendix C.2 (Eq. 3-4) to filter labels; affects which edges/nodes are supervised.
  • SRAM resistance percentile clip points = p1 and p99 of log10(Reff) in training split
    Eq. 9-10, data-dependent normalization from training split; affects label scale for regression/classification.
  • Classification boundaries = 0.2, 0.4, 0.6, 0.8
    Fixed by hand (Eq. 15) to define five magnitude classes.
  • Analog normalization maxima = M_R, M_C from training split
    Eq. 11-14, training-split maxima; chosen data-dependent constants used for label scaling.
assumptions (4)
  • domain assumption Effective resistance labels computed via Cholesky-inverse method [24] accurately represent post-layout parasitic behavior.
    Relied on in Section 3.3 and Algorithm 1 to generate edge labels; no validation against full SPICE or field-solver results is reported.
  • domain assumption Commercial extraction tools (Calibre xRC, StarRC) and tape-out-proven layouts provide ground-truth parasitics.
    Section 3.2 asserts ground truth; no independent audit or data license detail is given.
  • domain assumption Schematic-level aggregated features are sufficient to predict layout-dependent parasitics.
    Section 3.4 argues connectivity/geometry proxies for parasitics; the entire pre-layout prediction task presupposes this learnability.
  • domain assumption Lumping distributed RC networks into per-net Cg and per-pair Reff preserves the task-relevant physics.
    Section 3.3 states the reduction keeps key timing/noise characteristics; no quantitative validation of the simplification is provided.

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Cite this review

Pith. "Pith review of ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuits." pith.science (2026). https://pith.science/paper/B2LJPKQL

@misc{pith2026260723225,
  author       = {Pith},
  title        = {Pith review of: ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuits},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/B2LJPKQL}},
  note         = {Machine review of arXiv:2607.23225}
}
read the original abstract

As chip manufacturing processes advance to deep submicron nodes, parasitic interconnect effects increasingly dominate the performance of analog and mixed-signal (AMS) circuits and often lead to costly layout iterations. This makes early-stage estimation of parasitic capacitance and resistance important for parasitic-aware design exploration before full physical implementation. However, progress on GNN-based parasitic modeling has been hindered by the lack of public, high-fidelity RC benchmarks that support reproducible evaluation. To address this gap, we introduce ParasGB, the first open-source benchmark suite for pre-layout parasitic parameter prediction on circuit graphs. ParasGB provides large-scale, heterogeneous RC networks extracted with commercial EDA tools from tape-out-proven designs, together with a unified evaluation protocol covering node-level ground capacitance, edge-level resistance, and edge-level coupling capacitance. Within this framework, we benchmark diverse GNN architectures using a standardized training pipeline and expose challenges such as extreme label imbalance, long-tailed parasitic distributions, and strong structural heterogeneity. By establishing a physically grounded and standardized benchmark for early-stage parasitic prediction, ParasGB provides an open platform for reproducible research on circuit graph learning and parasitic-aware model development. All datasets, preprocessing scripts, and configurations are publicly available in our code repository https://github.com/ShenShan123/ParasGB.git.

Figures

Figures reproduced from arXiv: 2607.23225 by the authors.

Figure 1
Figure 1. Comparison between traditional AMS design flow [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. SRAM circuit graph conversion: (a) The schematic. (b) Post-layout netlist with extracted RCs by StarRC. (c) Our [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Label Distributions for ParasGB-SRAM and ParasGB-Analog. The pronounced data imbalance poses significant [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figures from the paper (6 more)
Figure 4
Figure 4. Figure 4: Overview of 20 Analog Circuit Effective Resistance Label Distribution [PITH_FULL_IMAGE:figures/full_fig_p013_4.png]
Figure 5
Figure 5. Figure 5: Overview of 6 SRAM Circuit Coupling Capacitance Label Distribution [PITH_FULL_IMAGE:figures/full_fig_p013_5.png]
Figure 6
Figure 6. Figure 6: Overview of 6 SRAM Circuit Effective Resistance Label Distribution [PITH_FULL_IMAGE:figures/full_fig_p014_6.png]
Figure 7
Figure 7. Figure 7: Overview of 20 Analog Circuit Ground Capacitance Label Distribution [PITH_FULL_IMAGE:figures/full_fig_p014_7.png]
Figure 8
Figure 8. Figure 8: Overview of 6 SRAM Circuit Ground Capacitance Label Distribution [PITH_FULL_IMAGE:figures/full_fig_p015_8.png]
Figure 9
Figure 9. Figure 9: analog circuit graph conversion: (a) The schematic. (b) Post-layout netlist with extracted RCs by StarRC. (c) Our [PITH_FULL_IMAGE:figures/full_fig_p015_9.png]

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Pith tools

Reviewed August 1, 2026 · model on record in the stance chip above.