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REVIEW 3 major objections 7 minor 1 cited by

Improving Figures of Merit for Quantum Circuit Compilation

T0 review · 3 major / 7 minor · reviewed 2026-08-10 · deepseek-v4-flash

Pith's one-line read Established circuit-quality metrics predict QPU execution only weakly; a machine-learning figure of merit trained on Hellinger distance beats them by 49%.

desk verdict Useful first correlation study of standard figures of merit against real QPU output error, but the headline ML improvement is likely overstated because the label may be dominated by finite-shot statistics and the comparison mixes full-set with held-out correlations. read the letter →

arxiv 2501.13155 v1 pith:C7AKTMUT submitted 2025-01-22 quant-ph

classification quant-ph
keywords quantumcircuitcompilationfiguresofmeritmachinelearningHellingerdistancerandomforestdepthQPUexecutionqualityPearsoncorrelation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper asks how well standard proxies for quantum circuit quality—gate count, circuit depth, expected fidelity, and estimated success probability—predict how a compiled circuit actually performs on a real quantum processor. Using 222 benchmark circuits run on two 20-qubit superconducting QPUs, the authors measure execution quality as the Hellinger distance between the noiseless simulated output and the QPU's empirical output distribution. They find that even the best established metric reaches only a Pearson correlation of 0.73 with that distance. They then train a random-forest regressor on a depth-independent, 30-feature circuit encoding to predict the Hellinger distance directly, achieving correlations of 0.88 and 0.94 on the two devices (0.91 combined), a 49% average improvement over the established figures of merit. The practical stake is that compilers could use such a learned figure of merit to choose circuit variants that genuinely execute better, rather than ones that merely look better on paper.

What carries the argument

The central object is the Hellinger distance $d(P,Q)$ between the true noiseless output distribution $P$ and the QPU's empirical output distribution $Q$, which serves as the ground-truth label for execution quality. The model is a random-forest regressor trained on a 30-dimensional, depth-independent feature encoding of the compiled circuit; the predictive features include liveness, gate ratios, parallelism, directed program communication, gate counts, and circuit depth. The model is evaluated by the Pearson correlation coefficient between its predicted values and the measured Hellinger distances on held-out circuits, and the same coefficient is used to score the established figures of merit against the same ground truth.

What would settle it

Execute the same benchmark set on a third QPU, or on the same QPU after a recalibration, and compare the trained model's predictions against Hellinger distances measured with a much larger number of shots; if the Pearson correlation drops to the 0.7 level or the ranking of circuit variants changes, the proposed figure of merit's generalization claim fails.

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Extended reading notes

Core claim

The paper's central claim is that the commonly used figures of merit for quantum circuit compilation—gate count, circuit depth, expected fidelity, and estimated success probability—correlate only weakly with real execution quality, and that a machine-learning model trained on circuit features can approximate that quality much more accurately. Execution quality is operationalized as the Hellinger distance between the ideal output distribution from a noiseless simulation and the empirical distribution from executing the circuit on a QPU. On a case study with two 20-qubit devices, the authors report Pearson correlations of 0.46–0.61 for gate count, 0.46–0.62 for depth, 0.66–0.80 for expected fidelity, and 0.59–0.70 for ESP, whereas their proposed model reaches 0.88 and 0.94 on the two devices and 0.91 combined. The authors conclude that selecting and combining circuit features—especially liveness, gate ratios, parallelism, and directed program communication—yields a figure of merit that is substantially more aligned with actual execution quality than any single established measure.

Load-bearing premise

The paper equates 'actual execution quality' with the Hellinger distance between the noiseless simulated output distribution and the empirical QPU shot distribution; if that distance is not the right target, or if finite-shot estimates make the labels noisy, the reported correlations lose their meaning.

Editorial extensions

If this is right

  • A compiler that optimizes for the learned figure of merit instead of gate count or depth should, if the correlation holds, produce circuits whose executed output distributions are closer to the ideal.
  • The study indicates that more complex calibration-based metrics are not automatically better; outdated T1 and T2 data can make ESP less predictive than expected fidelity.
  • The trained model can serve as a QPU-specific figure of merit that needs no calibration data at inference time, only the circuit's feature vector.
  • Feature-importance analysis suggests that qubit-activity and interaction features carry the predictive signal, so future compilation heuristics should emphasize those rather than raw gate counts.
  • Because the model is trained on classically simulable circuits, scaling to larger circuits will require a simulation-free label such as the probability of successful trials.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The Hellinger distance treats every output bitstring error equally; an application that cares only about specific observables might rank circuits differently, so the learned metric may not be the best objective for every algorithm.
  • The 49% improvement is measured on two devices from the same family; on other architectures with different noise physics, the feature importances and correlations could shift, so the claim should be re-tested per architecture.
  • The model is trained on past QPU executions; as device noise drifts, its correlation likely degrades until retraining, which is an implicit cost the paper does not quantify.
  • The same feature vector could be used not merely to rank compiled circuits but as a reward signal inside compilation search (e.g., pass ordering or qubit-mapping scoring), an extension the paper does not explore.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 7 minor

Summary. The paper assesses how well established circuit figures of merit (gate count, depth, expected fidelity, and ESP) track a proposed measure of execution quality, defined as the Hellinger distance between a noiseless state-vector simulation and the empirical output distribution obtained on a real QPU (Eq. (1)). It then trains a random-forest regressor on a 30-dimensional, depth-independent circuit encoding from MQT Predictor to predict this distance, and evaluates the resulting figure of merit on a held-out test set of circuits executed on two 20-qubit IQM devices (Q20-A and Q20-B). The reported Pearson correlations are 0.88, 0.94, and 0.91 for the two devices and their combination, respectively, with an average improvement of 49% over the established figures of merit (Table I, Section V.C). The implementation is released as part of the open-source MQT Predictor.

Significance. The practical contribution would be real if the label is faithful and the comparison is consistent: an inference-time figure of merit that needs no calibration data, uses a fixed-size feature vector, and is trained once per QPU is attractive for compilation flows, and the feature-importance analysis gives interpretable guidance. The use of real QPU executions and the public code are clear strengths. I do not regard the use of Hellinger distance as both training label and evaluation metric as circular, because the proposed model is assessed out-of-sample; however, the current manuscript does not yet establish that the Hellinger label is a stable, hardware-meaningful target, nor that the headline comparison is made on equal footing.

major comments (3)
  1. [Sec. IV.A, Eq. (1); Sec. V.A] The manuscript never reports the number of shots (or repeated executions) used to form the empirical QPU distribution Q. For a finite number of shots n, even a noiseless device yields a positive expected Hellinger distance from P that grows with the support size of P; for large output supports this finite-sample floor can dominate. Because features such as liveness, parallelism, gate ratios, and directed program communication can correlate with how spread out the true distribution is, the random forest may partly be predicting finite-sample statistical distance rather than hardware-induced error. Please report the shot count, repeat executions to estimate the variability of the label, and show that the reported correlations survive this finite-sample baseline.
  2. [Sec. V.B, Sec. V.C, Table I] The correlation coefficients in the first four rows of Table I are computed on the entire 222-circuit benchmark set, whereas the last row is computed only on the held-out 20% test set. Because Pearson correlation depends on the sample composition and size, this is not an apples-to-apples comparison and the stated 49% improvement is not yet supported. Compute all figures of merit on the same held-out test set (or use cross-validated predictions for every figure of merit) and report the number of test circuits used.
  3. [Sec. V.C] No confidence intervals or significance tests are reported for any correlation in Table I. With roughly 44 held-out circuits per QPU, the uncertainty in the proposed correlations is non-negligible; intervals are needed to judge whether the gap to expected fidelity (0.88 vs. 0.66 on Q20-A) and the 49% average improvement are meaningful. Please also clarify how the 'Combined' column is computed for the proposed approach, i.e., whether it pools predictions from two QPU-specific regressors or uses a single model.
minor comments (7)
  1. [Sec. V.B] The text says ESP achieves 0.78 on Q20-B, but Table I reports 0.70; please correct the inconsistency.
  2. [Eq. (1)] The notation in Eq. (1) is hard to parse: p_{|i\rangle} and q_{|i\rangle} should be written as p_i and q_i with an explicit index, and the square-root signs should be clarified.
  3. [Sec. V.A] The phrase 'cross-validation over three training sets' is ambiguous; please specify the number of folds and whether the hyperparameter grid search is nested within the training folds.
  4. [Sec. IV.B and Sec. V.A] The 'revised version of the circuit encoding introduced in [40]' is central to the method but is not described; please summarize the 30 features or at least state exactly where their definition can be found.
  5. [Sec. V.D] The statement that the model 'does not directly rely on device-specific measurement data' should be qualified, since the training labels require QPU executions; only inference is calibration-free.
  6. [Fig. 3] The feature-importance plot lacks error bars and leaves 'Other features' unspecified; please state how importances are computed (e.g., permutation importance versus impurity-based importance) and what the 'other' features are.
  7. [Sec. V.A] 'Qiskit Aear' is a typo for 'Qiskit Aer'.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the ML figure of merit is an out-of-sample estimator of an independently measured Hellinger distance, not a restatement of its training target.

full rationale

The paper's derivation chain is a standard supervised-learning pipeline. The label, the Hellinger distance d(P,Q) of Eq. (1), is defined independently from a noiseless simulation P and empirical QPU distribution Q, not from the model or from any figure of merit. The random forest is trained on these labels for a training subset and then evaluated on a held-out test set; Section V.A states an '80/20 train-test ratio' and Section V.C reports correlations for 'the unseen circuit test set.' Thus the reported Pearson correlations are out-of-sample predictions, not identities or fitted values renamed as predictions. The self-citations to MQT Predictor [40] and MQT Bench [43] supply the feature encoding and benchmark circuits, but they do not justify the central empirical claim that the trained model correlates with execution quality; that claim is tested against independently obtained QPU execution results. There is no invoked uniqueness theorem, no ansatz smuggled in via citation, and no known result merely renamed. Concerns about finite-shot noise or label stability are validity/correctness risks, not circularity, and cannot be scored as a circular step under the stated rules. The comparison against established figures of merit on the same real-QPU data further makes the evaluation externally anchored. Overall, no step in the derivation reduces by construction or by self-citation to its own inputs.

Assumptions & free parameters 3 free parameters · 6 assumptions · 0 invented entities

No new physical entities are introduced. The free parameters are the random forest hyperparameters, the train-test split, and the depth cutoff. The axioms are mostly domain assumptions about the representativeness of the benchmark and the adequacy of the chosen metrics and features. The feature encoding is taken from prior work by the same group, which is a source of potential circularity but not a new entity.

free parameters (3)
  • Random forest hyperparameters (number of trees, max depth, min samples per leaf and split) = Not reported
    Tuned via grid search (Section V.A.3) on validation data. The specific values are not given, but they affect the model and its correlation.
  • Train-test split ratio 80/20 = 80/20
    Chosen by hand in Section V.A.3. The split affects the reported test-set correlation and is not justified.
  • Circuit depth cutoff (1000) = 1000
    Circuits with compiled depth above 1000 were excluded (Section V.A.1), leaving 222 circuits. This selection threshold shapes the benchmark set and the results.
assumptions (6)
  • domain assumption Hellinger distance between the true and QPU output distributions is an appropriate operationalization of execution quality.
    Used as the label for training and as the comparison target for all figures of merit. If this metric does not capture what compilers should optimize, the whole study is affected.
  • domain assumption The MQT Bench circuits with depth below 1000 are representative of practical quantum circuits.
    The study's conclusions about weak correlations and the trained model's performance rest on this benchmark set. Deep or larger circuits are excluded.
  • domain assumption The state-vector simulation gives the exact noiseless distribution.
    True distributions are obtained from a noiseless simulator, which is reliable for up to 20 qubits but assumes the simulator exactly matches the intended unitary.
  • ad hoc to paper The 30-dimensional feature encoding from [40] contains sufficient information to predict the Hellinger distance.
    The proposed model's performance depends entirely on this feature set. The paper lists feature names but does not define them in full, relying on a self-cited reference.
  • ad hoc to paper Random forest regression is a suitable model class for this prediction task.
    No comparison with other regressors is given, but the authors choose random forest and validate it with cross-validation.
  • domain assumption QPU noise characteristics remain stable during data collection.
    The paper does not address temporal drift of calibration parameters, which is acknowledged as future work in Section V.D.

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Cite this review

Pith. "Pith review of Improving Figures of Merit for Quantum Circuit Compilation." pith.science (2026). https://pith.science/paper/C7AKTMUT

@misc{pith2026250113155,
  author       = {Pith},
  title        = {Pith review of: Improving Figures of Merit for Quantum Circuit Compilation},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/C7AKTMUT}},
  note         = {Machine review of arXiv:2501.13155}
}
read the original abstract

Quantum computing is an emerging technology that has seen significant software and hardware improvements in recent years. Executing a quantum program requires the compilation of its quantum circuit for a target Quantum Processing Unit (QPU). Various methods for qubit mapping, gate synthesis, and optimization of quantum circuits have been proposed and implemented in compilers. These compilers try to generate a quantum circuit that leads to the best execution quality - a criterion that is usually approximated by figures of merit such as the number of (two-qubit) gates, the circuit depth, expected fidelity, or estimated success probability. However, it is often unclear how well these figures of merit represent the actual execution quality on a QPU. In this work, we investigate the correlation between established figures of merit and actual execution quality on real machines - revealing that the correlation is weaker than anticipated and that more complex figures of merit are not necessarily more accurate. Motivated by this finding, we propose an improved figure of merit (based on a machine learning approach) that can be used to predict the expected execution quality of a quantum circuit for a chosen QPU without actually executing it. The employed machine learning model reveals the influence of various circuit features on generating high correlation scores. The proposed figure of merit demonstrates a strong correlation and outperforms all previous ones in a case study - achieving an average correlation improvement of 49%.

Figures

Figures reproduced from arXiv: 2501.13155 by the authors.

Figure 1
Figure 1. Compilation of a quantum circuit demonstrating (a) mapping, (b) synthesis, and (c), (d) optimization passes for a [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Workflow for feature and label generation from a com [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Random forest model feature importance. average correlation of all previous figures of merit over both QPUs (last column), the proposed figure of merit outperforms their correlation scores by 49%. In order to understand how the proposed figure of merit managed to capture the execution quality so well, we investigate the model’s feature importance depicted in [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗

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Pith tools

Reviewed August 10, 2026 · model on record in the stance chip above.