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Hardware-Assisted Parameterized Circuit Execution

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arxiv 2409.03725 v2 pith:DU7SIW4U submitted 2024-09-05 quant-ph

classification quant-ph
keywords circuitscircuitdifferentexecutionhardwareparameterizedquantumclasses
verification ladder T0 review T1 audit T2 compute T3 formal
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Standard compilers for quantum circuits decompose arbitrary single-qubit gates into a sequence of physical X(pi/2) pulses and virtual-Z phase gates. Consequently, many circuit classes implement different logic operations but have an equivalent structure of physical pulses that only differ by changes in virtual phases. When many structurally-equivalent circuits need to be measured, generating sequences for each circuit is unnecessary and cumbersome, since compiling and loading sequences onto classical control hardware is a primary bottleneck in quantum circuit execution. In this work, we develop a hardware-assisted protocol for executing parameterized circuits on our FPGA-based control hardware, QubiC. This protocol relies on a hardware-software co-design technique in which software identifies structural equivalency in circuits and "peels" off the relevant parameterized angles to reduce the overall waveform compilation time. The hardware architecture then performs real-time "stitching" of the parameters in the circuit to measure circuits that implement a different overall logical operation. This work demonstrates significant speed ups in the total execution time for several different classes of quantum circuits.

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Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Efficient Classical Processing of Constant-Depth Time Evolution Circuits in Control Hardware

    quant-ph 2025-07 conditional novelty 6.0 of 10

    Using parameterized circuit execution on constant-depth Cartan time-evolution circuits cuts classical compilation and processing time for spin-spin correlation functions.

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