Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
End-to-end codesign of Hessian-aware quantized neural networks for FPGAs and ASICs
As of 11 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 2 inbound Pith citation observations for arXiv:2304.06745.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-11T06:34:44.6726+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-10T21:17:54.084352Z
A source-named dated measurement, never combined with another source.
Source: pith, observed 2026-08-10T21:17:54.173816Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation 2cde00c4-6893-4046-954f-71a739ddd268 · inbound
Neural Architecture Codesign for Fast Physics Applications cites this paper.
Neural Architecture Codesign for Fast Physics Applications End-to-end codesign of Hessian-aware quantized neural networks for FPGAs and ASICs
Reference 31
- Resolution
- verified exact
- local_arxiv, observed 2026-08-10T21:17:54.179075Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.
Observation c44bb760-c89d-4be9-ae28-4ed2664848e0 · inbound
wa-hls4ml: A Benchmark and Surrogate Models for hls4ml Resource and Latency Estimation cites this paper.
wa-hls4ml: A Benchmark and Surrogate Models for hls4ml Resource and Latency Estimation End-to-end codesign of Hessian-aware quantized neural networks for FPGAs and ASICs
Reference 9
- Resolution
- unresolved
- no resolver link, observed 2026-08-03T23:44:04.839552Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.