Paper Citation Record · LEDGER

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing

As of 17 August 2026, this Paper Citation Record lists 20 of 20 outbound references and 0 inbound Pith citation observations for arXiv:2608.12635.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2608.12635 v1

Coverage vector

measured 20 of 20 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-16T00:08:22.586199Z

measured 20 of 20 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-17T06:30:58.91139+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

20 of 20 outbound references displayed

verified exact8
verified fuzzy2
unresolved10
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 4c591e76-4e3b-42ea-9a5c-6b4357891d6e · outbound

This paper cites MetRex: A benchmark for Verilog code metric reasoning using LLMs.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing MetRex: A benchmark for Verilog code metric reasoning using LLMs

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T00:08:23.577879Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 22600bf7-6555-4768-90fb-db5928366b7a · outbound

This paper cites RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Experts.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Experts

Reference 2

Resolution: verified exact; local_arxiv, observed 2026-08-16T00:08:23.479135Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 80b4e30c-51b9-4f17-b638-86e6dbe8c6e2 · outbound

This paper cites SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design

Reference 3

Resolution: unresolved; no resolver link, observed 2026-08-16T00:08:22.457101Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation bba2b2cc-8c27-449c-aa98-86346565dee3 · outbound

This paper cites DeMillo, Richard J.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing DeMillo, Richard J

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-16T00:08:22.463791Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ae0646cd-4d84-447c-b5a9-b427ea37d066 · outbound

This paper cites Functional testbench qualification by mutation analysis.VLSI Design, 2015:256474, 2015.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing Functional testbench qualification by mutation analysis.VLSI Design, 2015:256474, 2015

Reference 5

Resolution: verified exact; doi, observed 2026-08-16T00:08:22.655912Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation e0bd818b-5f3b-41e5-aa56-6eb3503253d2 · outbound

This paper cites GRPO with state mutations: Improving LLM-based hardware test plan generation.arXiv preprint arXiv:2601.07593, 2026.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing GRPO with state mutations: Improving LLM-based hardware test plan generation.arXiv preprint arXiv:2601.07593, 2026

Reference 6

Resolution: verified exact; raw_fallback, observed 2026-08-16T00:08:23.329250Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 9ff95317-56f7-4491-8380-fbc94ddc4c68 · outbound

This paper cites VerilogEval: Evaluating Large Language Models for Verilog Code Generation.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-16T00:08:22.482762Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ddbc3ea5-1f4d-4be8-bff1-0d8271cd981d · outbound

This paper cites OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-16T00:08:22.489390Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 1106c16c-9584-4fcf-abbe-4ceb298612f5 · outbound

This paper cites RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-16T00:08:22.494120Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c31426c2-2a29-4db9-a2d4-bdfdb26e00af · outbound

This paper cites Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-16T00:08:22.502422Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2e96c36b-5071-44cc-8e34-8cbde36808e1 · outbound

This paper cites Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-16T00:08:22.507720Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 390f99aa-4f65-4756-80d4-8f32c4e23f32 · outbound

This paper cites ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis

Reference 12

Resolution: verified exact; local_arxiv, observed 2026-08-16T00:08:23.092167Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 16ac31ef-06f5-4209-bc0a-1eedab0aef26 · outbound

This paper cites AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-16T00:08:22.522912Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 13e3f751-e869-402a-a270-69465a40347c · outbound

This paper cites ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols

Reference 14

Resolution: verified exact; local_arxiv, observed 2026-08-16T00:08:23.025089Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation de2f58a2-155f-410f-b59b-259f33e8ebb2 · outbound

This paper cites ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation

Reference 15

Resolution: verified exact; local_arxiv, observed 2026-08-16T00:08:22.959005Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 2d8cc2c7-136f-473c-9ba7-77dc1e58211e · outbound

This paper cites RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models

Reference 16

Resolution: verified exact; local_arxiv, observed 2026-08-16T00:08:22.909224Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 5a7307a0-b131-4a80-987d-61484c45086b · outbound

This paper cites RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision

Reference 17

Resolution: verified exact; local_arxiv, observed 2026-08-16T00:08:22.851315Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 18c02be8-bd27-4b15-be65-ee9703af04e5 · outbound

This paper cites Mantra: Mutation testing of hardware design code based on real bugs.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing Mantra: Mutation testing of hardware design code based on real bugs

Reference 18

Resolution: unresolved; no resolver link, observed 2026-08-16T00:08:22.568906Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8237c536-c7bd-45c9-b4ac-95a94b56a1fe · outbound

This paper cites Introduction to Mutation Coverage with Yosys (MCY).

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing Introduction to Mutation Coverage with Yosys (MCY)

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-16T00:08:23.522081Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation a928f4af-56c1-46f8-b1d1-d6a1cf2aac05 · outbound

This paper cites ChipBench: A next-step benchmark for evaluating LLM performance in AI-aided chip design.arXiv preprint arXiv:2601.21448, 2026.

GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing ChipBench: A next-step benchmark for evaluating LLM performance in AI-aided chip design.arXiv preprint arXiv:2601.21448, 2026

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-16T00:08:22.586199Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Pith citing papers

No inbound Pith citation observations are available.