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Paper Citation Record · LEDGER

Learned Hardware/Software Co-Design of Neural Accelerators

As of 10 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 2 inbound Pith citation observations for arXiv:2010.02075.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2010.02075 v1

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 2 of 2 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-10T06:31:04.303077+00:00

measured 2 of 2 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-08T14:14:35.395499Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: pith, observed 2026-08-06T14:49:56.776182Z

Reference resolution

0 of 0 outbound references displayed

  • verified exact0
  • verified fuzzy0
  • unresolved0
  • parse uncertain0
  • malformed identifier0
  • metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 39ad9462-27af-42f6-a0ae-b7ac694bcc37 · inbound

Machine Learning Fleet Efficiency: Analyzing and Optimizing Large-Scale Google TPU Systems with ML Productivity Goodput cites this paper.

Machine Learning Fleet Efficiency: Analyzing and Optimizing Large-Scale Google TPU Systems with ML Productivity Goodput Learned Hardware/Software Co-Design of Neural Accelerators

Reference 2020

Resolution
unresolved
no resolver link, observed 2026-08-08T14:14:35.395499Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

source=pdf_text observed=2026-08-08T14:14:35.395499Z digest=sha256:a7ddac4d7e8c8cbc8364a80c7efd9111ca401c1d2c6bbd79f1317e0066ae18e3

Observation 87cb526e-9d16-4257-97e7-224704e1575f · inbound

FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design cites this paper.

FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Design Learned Hardware/Software Co-Design of Neural Accelerators

Reference 23

Resolution
verified exact
local_arxiv, observed 2026-08-06T14:49:56.781160Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-10T06:31:04.303077+00:00.

source=pdf_text observed=2026-08-06T14:49:56.601189Z digest=sha256:0db7d760f07d803274da1bb521ead0052b707ec5880c0cb20861e642659bd073