Paper Citation Record · LEDGER

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs

As of 15 August 2026, this Paper Citation Record lists 46 of 46 outbound references and 1 inbound Pith citation observation for arXiv:2502.08807.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2502.08807 v2

Coverage vector

measured 46 of 46 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-07T23:42:25.300663Z

measured 47 of 47 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-15T06:32:42.880941+00:00

measured 1 of 1 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-12T11:43:29.234890Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: pith, observed 2026-08-12T11:43:35.816362Z

Reference resolution

46 of 46 outbound references displayed

verified exact2
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External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 53832c10-45dc-476f-b045-09a7b3adc8c0 · outbound

This paper cites Unified language model pre-training for natural language understanding and generation,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Unified language model pre-training for natural language understanding and generation,

Reference 1

Resolution: unresolved; no resolver link, observed 2026-08-07T23:42:25.007904Z

Source-reported events for the cited work

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Observation 4936a231-d22f-4958-a908-5afb771ec831 · outbound

This paper cites An Image is Worth 16x16 Words: Transformers for Image Recognition at Scale.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs An Image is Worth 16x16 Words: Transformers for Image Recognition at Scale

Reference 2

Resolution: unresolved; no resolver link, observed 2026-08-07T23:42:25.013630Z

Source-reported events for the cited work

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Observation d439e947-47eb-4d4f-9fbf-a7256457e426 · outbound

This paper cites Llama 2: Open Foundation and Fine-Tuned Chat Models.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Llama 2: Open Foundation and Fine-Tuned Chat Models

Reference 3

Resolution: unresolved; no resolver link, observed 2026-08-07T23:42:25.018643Z

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Observation d344252a-ff5d-4cb1-b390-4967cab785bd · outbound

This paper cites A review on large language models: Architectures, applications, taxonomies, open issues and challenges,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs A review on large language models: Architectures, applications, taxonomies, open issues and challenges,

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:26.386648Z

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Observation d6a3531e-8b27-4d67-b96f-aac023854415 · outbound

This paper cites Attention is all you need,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Attention is all you need,

Reference 5

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Source-reported events for the cited work

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Observation 0ad047e4-893a-413c-8ea8-9e57e82a1ae4 · outbound

This paper cites Allo: A programming model for composable accelerator design,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Allo: A programming model for composable accelerator design,

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-07T23:42:25.034717Z

Source-reported events for the cited work

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Observation c5be5f49-28fe-414d-9b0c-3eea9bd3202a · outbound

This paper cites Flexcnn: An end-to-end framework for composing cnn accelerators on fpga,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Flexcnn: An end-to-end framework for composing cnn accelerators on fpga,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:26.322268Z

Source-reported events for the cited work

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Observation 0205b166-9cc7-41b1-ad5b-7c889a5df0bb · outbound

This paper cites Tpu v4: An optically reconfigurable supercomputer for machine learning with hardware sup- port for embeddings,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Tpu v4: An optically reconfigurable supercomputer for machine learning with hardware sup- port for embeddings,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:26.293988Z

Source-reported events for the cited work

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Observation 4bf31d73-71d8-42e4-a908-ea55578635c2 · outbound

This paper cites Fet-opu: A flexible and efficient fpga-based overlay processor for transformer networks,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Fet-opu: A flexible and efficient fpga-based overlay processor for transformer networks,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:26.260975Z

Source-reported events for the cited work

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Observation 3de44d2a-8c84-4b41-9afe-47c06bdba333 · outbound

This paper cites Hardware acceleration of fully quantized bert for efficient natural language processing,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Hardware acceleration of fully quantized bert for efficient natural language processing,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:26.239036Z

Source-reported events for the cited work

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Observation 3d128b80-c527-447e-ac6b-eba0da348057 · outbound

This paper cites Dnnexplorer: a framework for modeling and exploring a novel paradigm of fpga-based dnn accelerator,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Dnnexplorer: a framework for modeling and exploring a novel paradigm of fpga-based dnn accelerator,

Reference 11

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Observation 6a40b328-d28d-445d-a2dd-613240757282 · outbound

This paper cites Understanding the potential of fpga-based spatial accel- eration for large language model inference,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Understanding the potential of fpga-based spatial accel- eration for large language model inference,

Reference 12

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Source-reported events for the cited work

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Observation 3763345c-11bd-4b37-a280-b3e480e9c7e7 · outbound

This paper cites Ssr: Spatial sequential hybrid architecture for latency throughput tradeoff in transformer acceleration,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Ssr: Spatial sequential hybrid architecture for latency throughput tradeoff in transformer acceleration,

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:26.151949Z

Source-reported events for the cited work

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Observation 1708985e-c13e-4701-81ba-5c95d188a7b8 · outbound

This paper cites Language models are unsupervised multitask learners,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Language models are unsupervised multitask learners,

Reference 14

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Source-reported events for the cited work

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Observation 4dd33f58-5519-4ff6-9335-11905e437a9c · outbound

This paper cites Deep residual learning for image recognition,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Deep residual learning for image recognition,

Reference 15

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Source-reported events for the cited work

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Observation 72248158-c86b-48f8-bf5a-c4c35bda9203 · outbound

This paper cites Aggregated residual transformations for deep neural networks,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Aggregated residual transformations for deep neural networks,

Reference 16

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Source-reported events for the cited work

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Observation 201709a1-09e0-46bd-8c12-ca22fa02b136 · outbound

This paper cites Inter-layer scheduling space definition and exploration for tiled accelerators,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Inter-layer scheduling space definition and exploration for tiled accelerators,

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:26.062970Z

Source-reported events for the cited work

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Observation 9bdeb9fd-b944-4097-ac42-89b8a84d815a · outbound

This paper cites A fully pipelined and dynamically composable architecture of cgra,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs A fully pipelined and dynamically composable architecture of cgra,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:26.044366Z

Source-reported events for the cited work

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Observation 99c067da-4756-4c21-b8ce-56b7361fd1f9 · outbound

This paper cites A multi-neural network acceleration architecture,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs A multi-neural network acceleration architecture,

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:26.025472Z

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Observation c11509df-73d0-4dbb-87c5-1ff99250d546 · outbound

This paper cites Overgen: Improving fpga usability through domain-specific overlay generation,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Overgen: Improving fpga usability through domain-specific overlay generation,

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:26.008760Z

Source-reported events for the cited work

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Observation 80a7fb2b-69cb-4299-9955-56cd0fe13943 · outbound

This paper cites Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays

Reference 21

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Source-reported events for the cited work

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Observation 435fdf56-4f10-4e06-9437-1ecd030695d3 · outbound

This paper cites Fpga hls today: successes, challenges, and opportunities,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Fpga hls today: successes, challenges, and opportunities,

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.988116Z

Source-reported events for the cited work

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Observation 431d877f-51cd-4332-b032-b918e0239b49 · outbound

This paper cites Dfx: A low-latency multi-fpga appliance for accelerating transformer-based text generation,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Dfx: A low-latency multi-fpga appliance for accelerating transformer-based text generation,

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.967427Z

Source-reported events for the cited work

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Observation e9c9316e-b0ab-4fc6-8815-cd5037e62bda · outbound

This paper cites GenGNN: A Generic FPGA Framework for Graph Neural Network Acceleration.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs GenGNN: A Generic FPGA Framework for Graph Neural Network Acceleration

Reference 24

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Observation 45916175-f94d-4e66-afb5-6ed0404537f6 · outbound

This paper cites ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network

Reference 25

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Observation 9b3fb62f-6064-4af4-a5f0-eba03aa4374c · outbound

This paper cites Flightllm: Efficient large language model inference with a complete mapping flow on fpgas,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Flightllm: Efficient large language model inference with a complete mapping flow on fpgas,

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.942947Z

Source-reported events for the cited work

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Observation 6520112e-b067-45a5-b67d-0321a1595ebd · outbound

This paper cites A cgra-based approach for accelerating convolutional neural networks,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs A cgra-based approach for accelerating convolutional neural networks,

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.912977Z

Source-reported events for the cited work

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Observation 85c013a3-3c42-47d8-955f-aa17b2424073 · outbound

This paper cites Impact of fpga architecture on area and performance of cgra overlays,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Impact of fpga architecture on area and performance of cgra overlays,

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.892994Z

Source-reported events for the cited work

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Observation 20272ffa-61e4-494d-a8c5-0c758c2724d7 · outbound

This paper cites Fpga dynamic and partial reconfiguration: A survey of architectures, methods, and applications,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Fpga dynamic and partial reconfiguration: A survey of architectures, methods, and applications,

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.873951Z

Source-reported events for the cited work

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Observation 7d267a23-ae44-43a9-8b02-8cf19bec8650 · outbound

This paper cites Feather: A reconfigurable accelerator with data reordering support for low-cost on-chip dataflow switching,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Feather: A reconfigurable accelerator with data reordering support for low-cost on-chip dataflow switching,

Reference 30

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.850563Z

Source-reported events for the cited work

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Observation 6650bc73-1f32-4ed9-8dc8-c23418ffce0d · outbound

This paper cites Opu: An fpga-based overlay processor for convolutional neural networks,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Opu: An fpga-based overlay processor for convolutional neural networks,

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.828892Z

Source-reported events for the cited work

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Observation 4dd9b3e7-5b9d-44b7-8dca-1f241df80db9 · outbound

This paper cites Light-opu: An fpga-based overlay processor for lightweight convolutional neural networks,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Light-opu: An fpga-based overlay processor for lightweight convolutional neural networks,

Reference 32

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Observation b9cafa13-e6b8-485c-aed8-75a46a948486 · outbound

This paper cites Deep Learning with Dynamic Computation Graphs.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Deep Learning with Dynamic Computation Graphs

Reference 33

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This paper cites Alveo u280 data center accelerator card data sheet.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Alveo u280 data center accelerator card data sheet

Reference 34

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.780269Z

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This paper cites Amd versal hbm series product selection guide.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Amd versal hbm series product selection guide

Reference 35

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.755364Z

Source-reported events for the cited work

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Observation 331af8a5-9f7f-4d48-8e15-259fd14ebbbc · outbound

This paper cites A survey on vision transformer,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs A survey on vision transformer,

Reference 36

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.736544Z

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Observation a29e5557-0233-4975-b0ce-209d971aba31 · outbound

This paper cites Graph Attention Networks.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Graph Attention Networks

Reference 37

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This paper cites Yolov3: An incremental improvement,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Yolov3: An incremental improvement,

Reference 38

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.713862Z

Source-reported events for the cited work

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Observation 3183cde4-0489-44b6-ba29-2e3ee016acba · outbound

This paper cites Vgg convolutional neural networks practical,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Vgg convolutional neural networks practical,

Reference 39

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.692719Z

Source-reported events for the cited work

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Observation 6faf79d8-df27-4083-b0bf-d2d43c37c1cf · outbound

This paper cites Zero-vae-gan: Generating unseen features for generalized and trans- ductive zero-shot learning,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Zero-vae-gan: Generating unseen features for generalized and trans- ductive zero-shot learning,

Reference 40

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.674303Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation fc2a5d22-134c-4dec-b66d-3f3e4c4ec017 · outbound

This paper cites Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software- Programmable FPGAs,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software- Programmable FPGAs,

Reference 41

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.652510Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation ecf333e5-192c-40c9-a215-731fed065beb · outbound

This paper cites Polybench: The polyhedral benchmark suite,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Polybench: The polyhedral benchmark suite,

Reference 42

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.623350Z

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No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 7767e708-8e8a-41e7-a700-4eef366ff280 · outbound

This paper cites Tapa: a scalable task-parallel dataflow programming framework for modern fpgas with co-optimization of hls and physical design,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Tapa: a scalable task-parallel dataflow programming framework for modern fpgas with co-optimization of hls and physical design,

Reference 43

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.590717Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation c0f13032-f6b0-451c-96bd-19af638f6ed1 · outbound

This paper cites Fast inference of deep neural networks in FPGAs for particle physics,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Fast inference of deep neural networks in FPGAs for particle physics,

Reference 44

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Source-reported events for the cited work

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Observation a256145c-1d33-4a18-bf64-1ef6ebc76d8c · outbound

This paper cites Amd versal premium series product selection guide.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Amd versal premium series product selection guide

Reference 45

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.555475Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 67fda3b8-2ae5-4896-8321-bc7833172cc0 · outbound

This paper cites Autobridge: Coupling coarse-grained floorplanning and pipelining for high-frequency hls design on multi-die fpgas,.

InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs Autobridge: Coupling coarse-grained floorplanning and pipelining for high-frequency hls design on multi-die fpgas,

Reference 46

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T23:42:25.534013Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Pith citing papers

Observation 7efeefde-0d10-4482-8b15-d58aad6f22ac · inbound

Reconfigurable Stream Network Architecture cites this paper.

Reconfigurable Stream Network Architecture InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs

Reference 43

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