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REVIEW 3 major objections 5 minor 25 references

Quantum Circuit Transformation Based on Simulated Annealing and Heuristic Search

T0 review · 3 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read Using simulated annealing for the initial qubit placement and a grandchild look-ahead search for routing, the paper reports a 57% average reduction in added gates on a 20-qubit device.

desk verdict Solid heuristic engineering for NISQ qubit routing, but the abstract's 57% figure is an added-gate reduction, not a total-size reduction; the underlying 17.7% total-size gain is still real and worth publishing after fixes. read the letter →

arxiv 1908.08853 v1 pith:S5QU6LG2 submitted 2019-08-23 quant-ph

Xiangzhen Zhou , Sanjiang Li , Yuan Feng This is my paper · ORCID
classification quant-ph
keywords quantumcircuittransformationqubitmappingsimulatedannealingheuristicsearchlook-aheadNISQSWAPinsertionarchitecturegraph
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Real quantum chips only allow two-qubit gates between specific adjacent physical qubits, so an ideal circuit must be rewritten by inserting SWAP and Hadamard gates that move qubits around. This paper claims that the amount of inserted hardware can be sharply reduced by separating the task into two phases: simulated annealing chooses an initial logical-to-physical qubit placement that minimizes the total CNOT-implementation distance over a selected subset of gates, and a heuristic search then routes the remaining gates by looking one step beyond each candidate move. On a 20-qubit Tokyo device the algorithm adds 57.28% fewer elementary gates on average than the best previous mapping method, while running in polynomial time and quadratic space in the number of architecture edges. If the claim is right, the same circuits can be run on today's noisy hardware with less accumulated error, and larger circuits become compilable in practice.

What carries the argument

The load-bearing object is the CNOT distance $\mathrm{dist}_{\mathrm{cnot}}(v,v')$, defined as the fewest auxiliary CNOT and Hadamard gates needed to implement a CNOT between physical qubits $v$ and $v'$ in a given architecture graph; for an undirected graph of distance $d$ it is $3(d-1)$, and for a directed graph it is $7(d-1)$ or $7(d-1)+4$ depending on whether a shortest path already has the correct direction. This distance supplies both the simulated-annealing cost for the initial mapping and the layer-weighted heuristic cost in Eq. (4). The argument is carried by the double look-ahead: every candidate child state is scored by the best of its grandchildren, so the search avoids committing to a child whose short-term gain hides a poor next step. A remote-CNOT fallback and a pruning rule keep the search terminating in polynomial time.

What would settle it

Re-run the benchmark suite on the 20-qubit Tokyo architecture with several explicit subset rules for $C^*$—the first $k$ gates, a uniformly random sample of $k$ gates, the last $k$ gates, and all gates—and compare added-gate totals against the reverse-traversal baseline. If the 57.28% average reduction does not persist across these transparent subset choices, or if some natural choice of $C^*$ changes the ranking, the central claim fails.

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Extended reading notes

Core claim

On the paper's own terms, the central claim is that the NP-hard transformation of a logical circuit into one that respects a chip's connectivity graph splits cleanly into an initial-placement problem and a routing problem. Simulated annealing solves the placement problem by minimizing a gate cost over a chosen subset $C^*$ of the logical circuit: the cost of a gate is $\mathrm{dist}_{\mathrm{cnot}}(\tau(q),\tau(q'))$, the number of auxiliary CNOT and Hadamard gates needed to implement the gate at the current physical locations. The routing problem is then solved by a depth-two heuristic search: from the current state, generate all child states reachable by one SWAP insertion or by flipping a CNOT direction with four Hadamard gates, generate their grandchildren, score each grandchild as gates already inserted plus a layer-weighted heuristic cost for the remaining circuit, and move to the child that owns the cheapest grandchild. Reported results are a 57.28% average reduction in added gates relative to the reverse-traversal baseline on the 20-qubit Tokyo architecture, a 13.36% average reduction relative to the $A^*$-based baseline on QX5, polynomial time, and space quadratic in the number of architecture edges.

Load-bearing premise

The whole reported advantage rests on the unstated rule for selecting the subset $C^*$ of gates used by the simulated-annealing initial mapping; if that subset is not representative of the circuit as a whole, the initial placement may not generalize and the benchmark improvements could shrink or reverse.

Editorial extensions

If this is right

  • On the 20-qubit Tokyo architecture, the algorithm's total added-gate count across the 24 benchmark circuits is 181,282 versus 220,312 for the reverse-traversal baseline, a 57.28% improvement.
  • On the 16-qubit QX5 architecture, the algorithm beats the $A^*$-based baseline by 13.36% on average and handles circuits up to 30,000 elementary gates within two minutes.
  • With look-ahead depth increased, output circuits get still smaller but runtime grows quickly; the paper's one-level look-ahead is the chosen trade-off.
  • The heuristic's layer weights are adjustable, so the same algorithm can be re-tuned for different architectures and circuit families without changing the search structure.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The double look-ahead selection rule is transferable: any graph rearrangement problem where a single swap is the unit move and future costs are layer-like could use the same child-owned-by-best-grandchild rule, not just quantum circuit transformation.
  • Since the cost function ignores gate error rates and decoherence, a natural follow-up is to replace the fixed layer weights with device-calibrated error weights; the size reductions reported might then translate into even larger fidelity gains, or reveal trade-offs.
  • The authors note the simulated-annealing output is not stable across runs; a concrete extension is to restart it several times and feed the best of several mappings into the search, which would test whether the 57% figure is sensitive to the randomness in the placement phase.
  • The choice of the gate subset $C^*$ in Eq. (3) is left unspecified; comparing subset rules (first $k$ gates, uniform sample, all gates) would show how much of the reported gain comes from the placement phase versus the routing phase.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes a quantum circuit transformation algorithm that first constructs an initial qubit mapping via simulated annealing and then performs a heuristic search with a two-level look-ahead to route CNOT gates under the connectivity constraints of IBM QX5 and IBM Q20. The authors report polynomial time complexity and quadratic space complexity, and they benchmark the method against the algorithms of Zulehner et al. [25], Li et al. [13], and Cowtan et al. [7]. The main quantitative claim in the abstract and introduction is that the method reduces the size of the output circuits by about 57% on average compared with the state-of-the-art algorithm on IBM Q20.

Significance. The algorithmic ingredients are well motivated and the paper provides a public code repository, polynomial runtime bounds, and benchmarks on a substantial set of realistic circuits. If the empirical claims are stated correctly, the work is a useful contribution to the NISQ circuit compilation literature. However, the headline '57% reduction of output circuit size' is not supported by the data in Table 4, because the reported improvement ratio is computed on the number of added auxiliary gates, not on total output size. In addition, the simulated-annealing initial mapping depends on an unspecified gate subset C* in Eq. (3), and the many hand-set parameters are not subjected to sensitivity analysis. These issues do not invalidate the underlying algorithm, but they must be fixed before the paper's central empirical claims can be accepted.

major comments (3)
  1. [Abstract, Section 1, Section 5, Table 4] The abstract and Section 1 claim that the method 'can reduce by 57% on average the size of the output circuits' compared with the algorithm in [13] on IBM Q20. However, Section 5 defines the improvement ratio as (ncomp - nours)/ncomp, where ncomp and nours are the numbers of added auxiliary gates, not the total output circuit sizes. Using the aggregate row of Table 4 (original 152170 gates, [13] 220312 gates, proposed 181282 gates), the reduction in total output circuit size is (220312 - 181282)/220312 ≈ 17.7%, while the 57.28% figure is the reduction in added gates: (68142 - 29112)/68142. The headline claim must be rewritten to refer to added-gate overhead, or the experiments must be recomputed with the total size metric that the abstract states.
  2. [Eq. (3), Algorithm 1, Section 4.2] The initial mapping is defined as the minimizer of the sum of gate costs over a subset C* of the logical circuit, but the paper never specifies how C* is selected. Algorithm 1 takes C* as an input without describing its construction, and Section 4.2 only says that using all gates would be 'unnecessary' because tail gates have little impact. Since the quality of the initial mapping is load-bearing for the final routing cost, and since Section 6 concedes that the SA initial mapping is 'not stable,' the selection rule for C* must be stated explicitly and its influence on the reported improvements should be evaluated.
  3. [Section 4.2, Section 4.3, Section 5, Section 6] The algorithm relies on several empirically chosen parameters: the simulated-annealing temperatures Tmax, Tmin, the cooling factor Delta, the repetition count R, the look-ahead layer count l, the heuristic weights w_k and ws in Eq. (4), and the fallback threshold K. The paper gives no sensitivity analysis and reports no variance across SA random seeds; the conclusion itself states that initial-mapping quality is unstable. Because the aggregate improvement in Table 4 is the paper's central quantitative result, the authors should report the spread of results across runs and justify the parameter choices, or explicitly limit the claims to the particular parameter configuration used.
minor comments (5)
  1. [Table 2] The row for decod24-v2 reads '43 52 85 52 100.00%', which appears to contain an extra value and an improvement that cannot be produced by the stated formula (added gates 9 vs. 9 would give 0%). Please correct the entry or the formatting.
  2. [Table 4] The row for alu-v0_27 reports original gates 36, algorithm [13] output 39, proposed output 42, and improvement -75.00%. Under the stated added-gate formula, the added gates are 3 and 6, giving (3-6)/3 = -100%. Please reconcile the table entry with the definition.
  3. [Section 5, Eq. (4)] The text in Section 5 says 'we set ... w4 = 0.4 x (DAG - 1) x Nswap in Eq. (4)', but Eq. (4) uses the symbol ws rather than w4. Please align the notation.
  4. [Eq. (4)] Eq. (4) sums over layers k=0 to l with weights w_k, but the text says '1 = w0 >= w1 >= ...' and does not state a value for w0. Please specify w0 explicitly, especially because the example in Table 1 uses w1 = 1, w2 = 0.8, w3 = 0.6, ws = 0.4 without mentioning w0.
  5. [Figure 5] The convergence of the simulated annealing procedure is shown for a single circuit (adr4-197). Since the quality of SA is stochastic and Section 6 reports instability, it would be helpful to state whether similar convergence behavior was observed for the other benchmarks or to report a summary statistic over multiple runs.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the transformation algorithm is self-contained; the reported benchmark improvements are external to the method's construction, though the abstract's 57% claim is a metric mismatch, not a circular step.

full rationale

The paper's derivation chain is self-contained. Gate cost (Eq. 2) is defined from the architecture graph's precomputed CNOT distance; the initial mapping (Eq. 3) minimizes that cost over a subset C* via simulated annealing; the heuristic completion cost (Eq. 4) is a layered estimate with empirically set weights; and the search cost (Eq. 5) combines actual auxiliary-gate overhead with that heuristic estimate. Every quantity is defined from the input circuit and architecture graph, not from the benchmark outcomes. The reported improvement over [13], [25], and [7] is obtained by running the algorithm on external benchmark circuits and comparing output sizes, so it is not an input to the construction. No load-bearing self-citation appears: the comparison algorithms are external prior work, and no uniqueness theorem or ansatz is imported from the authors' own prior papers. The paper's own stated limitations—an unspecified C*-selection procedure (Section 4.2) and admitted instability of the simulated-annealing initial mapping (Section 6)—are reproducibility or robustness concerns, not circularity. The abstract's '57% reduction in size' also does not match the Section 5 improvement ratio, which is defined on added gates rather than total output circuit size; that is a claim-support discrepancy, not a circular derivation. Accordingly, no circular step is exhibited and the score is 0.

Assumptions & free parameters 5 free parameters · 4 assumptions · 0 invented entities

The algorithm introduces no new physical entities. It relies on several hand-set numerical parameters (heuristic weights, SA temperatures, fallback threshold, look-ahead depth) and an unspecified gate subset C*. The backing assumptions are standard circuit identities and the CNOT-only simplification.

free parameters (5)
  • Heuristic weights w1, w2, w3, ws in Eq. (4) = w1=1, w2=0.8, w3=0.6, ws=0.4*(DAG-1)*Nswap
    Chosen empirically; no sensitivity analysis provided; the cost function ranking of states depends on these values.
  • Look-ahead layer count l = 3
    Fixed to 3; Fig. 10 shows deeper look-ahead improves quality but increases time, with no systematic selection of this value.
  • SA parameters Tmax, Tmin, Delta, R = Tmax=100, Tmin=1, Delta=0.98, R=100
    Set empirically in the Fig. 5 caption; no sensitivity study is reported, and SA acceptance probabilities depend on them.
  • Fallback threshold K = 0.5*DAG
    Set as 0.5 times the architecture diameter; no analysis of the optimal value is given.
  • C* gate subset for initial mapping = not specified
    The paper never states how many gates or which layers are used in Eq. (3); this selection directly affects the initial mapping quality.
assumptions (4)
  • domain assumption Input logical circuits consist only of CNOT gates after removing single-qubit gates (Section 3).
    Single-qubit gates are ignored for routing; if they impose ordering constraints, the dependency structure could change.
  • standard math The dependency graph and layer decomposition (Section 3.1) correctly capture gate execution order.
    Standard DAG scheduling assumption; no issue raised.
  • ad hoc to paper The heuristic cost function Eq. (4) with decreasing layer weights is a valid proxy for remaining routing cost.
    No derivation or independent validation is provided; the algorithm's state selection depends on this proxy.
  • standard math SWAP gate decompositions in Fig. 3 require 3 CNOTs for undirected architectures and 7 gates for directed QX5, and the CNOT distance formula is correct.
    Standard circuit identities, accepted from the cited literature [25].

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Cite this review

Pith. "Pith review of Quantum Circuit Transformation Based on Simulated Annealing and Heuristic Search." pith.science (2026). https://pith.science/paper/S5QU6LG2

@misc{pith2026190808853,
  author       = {Pith},
  title        = {Pith review of: Quantum Circuit Transformation Based on Simulated Annealing and Heuristic Search},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/S5QU6LG2}},
  note         = {Machine review of arXiv:1908.08853}
}
read the original abstract

Quantum algorithm design usually assumes access to a perfect quantum computer with ideal properties like full connectivity, noise-freedom and arbitrarily long coherence time. In Noisy Intermediate-Scale Quantum (NISQ) devices, however, the number of qubits is highly limited and quantum operation error and qubit coherence are not negligible. Besides, the connectivity of physical qubits in a quantum processing unit (QPU) is also strictly constrained. Thereby, additional operations like SWAP gates have to be inserted to satisfy this constraint while preserving the functionality of the original circuit. This process is known as quantum circuit transformation. Adding additional gates will increase both the size and depth of a quantum circuit and therefore cause further decay of the performance of a quantum circuit. Thus it is crucial to minimize the number of added gates. In this paper, we propose an efficient method to solve this problem. We first choose by using simulated annealing an initial mapping which fits well with the input circuit and then, with the help of a heuristic cost function, stepwise apply the best selected SWAP gates until all quantum gates in the circuit can be executed. Our algorithm runs in time polynomial in all parameters including the size and the qubit number of the input circuit, and the qubit number in the QPU. Its space complexity is quadratic to the number of edges in the QPU. Experimental results on extensive realistic circuits confirm that the proposed method is efficient and can reduce by 57% on average the size of the output circuits when compared with the state-of-the-art algorithm on the most recent IBM quantum device viz. IBM Q20 (Tokyo).

Figures

Figures reproduced from arXiv: 1908.08853 by the authors.

Figure 1
Figure 1. Hadamard, CNOT and SWAP gate (from left to right). [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Two architecture graphs for IBM QX architecture. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Some gate decomposition and transformation rules. [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (7 more)
Figure 4
Figure 4. Figure 4: On the left is an example for logical quantum circuit with only CNOT gates and right DAG repre [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: Convergence of the simulated annealing algorithm on circuit adr4-197 and IBM Q20, where the blue [PITH_FULL_IMAGE:figures/full_fig_p007_5.png]
Figure 6
Figure 6. Figure 6: The quantum circuit alu-v0_27 with all single qubit gates removed. [PITH_FULL_IMAGE:figures/full_fig_p009_6.png]
Figure 7
Figure 7. Figure 7: A test architecture graph AGtest. states of s, also shown in [PITH_FULL_IMAGE:figures/full_fig_p009_7.png]
Figure 8
Figure 8. Figure 8: Schematic for remote CNOT operations with 2 and 3 hops. Generalized form can be found in [16]. [PITH_FULL_IMAGE:figures/full_fig_p013_8.png]
Figure 9
Figure 9. Figure 9: Effectiveness of the pruning mechanism obtained by running exemplary circuits on IBM Q20, where [PITH_FULL_IMAGE:figures/full_fig_p013_9.png]
Figure 10
Figure 10. Figure 10: Experiments on IBM Q20 for different look-ahead depths. The vertical axis on the left is the ratio of [PITH_FULL_IMAGE:figures/full_fig_p016_10.png]

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Reference graph

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