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Measured Effectiveness of Deep N-well Substrate Isolation in a 65nm Pixel Readout Chip Prototype

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arxiv 1908.06182 v3 pith:ZHP2VGMV submitted 2019-08-16 physics.ins-det hep-ex

classification physics.ins-dethep-ex
keywords isolationanalogdigitalsubstratecircuitcircuitsdeepn-well
verification ladder T0 review T1 audit T2 compute T3 formal
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The same charge sensitive preamplifier and discriminator circuit with different isolation strategies has been tested to compare the isolation of both analog and digital circuits from the substrate of a 65nm bulk CMOS process to the isolation of only digital circuits, tying analog ground locally to the substrate. This study will show that the circuit with analog on the substrate and digital in deep N-well has better noise isolation between analog and digital.

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