Exothermic reactive bonding for semiconductor die assemblies and associated systems and methods

Kyle K. Kirby, Eagle, ID (US)

Exothermic reactive bonding for semiconductor die assemblies and associated systems and methods

T0 review · 1 major / 0 minor · reviewed 2026-05-15 · grok-4.3

Challenge this review Download PDF Read on USPTO ↗ Review JSON

Pith's one-line read A semiconductor die bonds via exothermic epoxy reaction inside a recessed moat surrounding a conductive pad.

desk verdict Patent filing sketches a moat-and-recessed-pad geometry for exothermic epoxy die bonding but supplies zero materials, thermal data, or validation. read the letter →

uspto us-12622335 published 2026-05-05 patents H01L 24/80H01L 24/08H01L 24/05H01L 25/0657H01L 25/18H01L 2224/05647H01L 2224/08145H01L 2224/80365

Kyle K. Kirby, Eagle, ID (US) This is my paper · ORCID

classification patentsH01L24/8024/0824/0525/065725/182224/056472224/081452224/80365

keywords semiconductordieexothermicepoxydielectricmoatconductivepadbondingreactiveassembly

checked against Cost.FunctionalEquation ZeroParameterComparisonLedger

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The patent presents a semiconductor die whose dielectric layer contains a recessed moat filled with a first epoxy compound whose upper surface lies flush with the dielectric. This epoxy is formulated to react exothermically with a matching second epoxy during assembly. A conductive pad sits inside the moat, its top surface recessed relative to the dielectric while its bottom connects to the integrated circuitry. The design aims to produce a controlled, localized bond that joins dies without external heat sources or risk to the underlying circuitry. If the reaction proceeds as described, the structure supplies both mechanical attachment and electrical continuity in one step.

What carries the argument

Recessed moat filled with exothermic epoxy surrounding a recessed conductive pad.

What would settle it

A fabricated test die assembled with the moat-and-epoxy structure shows either thermal damage to circuitry or bond failure under standard electrical and mechanical tests.

Watch

Extended reading notes

Core claim

The semiconductor die comprises a substrate with integrated circuitry, a dielectric layer whose upper surface includes a recessed moat filled with a first epoxy compound that reacts exothermically with a second epoxy compound, the first epoxy surface remaining coplanar with the dielectric, and a conductive pad laterally surrounded by the moat whose top surface is recessed while its bottom surface couples to the circuitry.

Load-bearing premise

The two epoxy compounds will produce a controlled exothermic reaction that forms a reliable bond without damaging circuitry or shifting alignment.

Editorial extensions

If this is right

Bonding occurs without external heat sources applied to the die stack.
The coplanar epoxy surface maintains planarity for subsequent processing steps.
The recessed pad ensures electrical contact forms only after the epoxy reaction begins.
The same moat geometry can be repeated across multiple dies in a stack or package.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Assembly lines could eliminate high-temperature ovens currently used for die attach.
Yield may rise in thin-wafer or high-density packaging where thermal budgets are tight.
The approach could be combined with existing epoxy dispensing equipment without new capital tools.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Desk Editor's Note

read the letter

The core claim is a dielectric layer with a coplanar moat of one epoxy surrounding a recessed conductive pad, so that a second epoxy can trigger a controlled exothermic reaction during stacking. That geometry is spelled out cleanly in the abstract and claim 1, and it does give a concrete way to keep the reaction zone away from the pad while maintaining planarity. The description is precise enough that a packaging engineer could sketch a mask set from it without guessing the layout intent. Beyond the geometry, however, the document contains nothing else. No epoxy chemistries are named, no enthalpy values or peak temperatures are given, and there are no bond-strength numbers, warpage measurements, or thermal-budget calculations. The assumption that the reaction stays inside safe limits for the underlying circuitry is simply asserted. Because this is a patent application rather than a research manuscript, the absence of data is expected, but it also means the functional performance remains unproven. A reader looking for new process ideas might still pull the moat-and-recess layout as a starting point for simulation work. Anyone needing evidence that the bond actually forms reliably or that the heat stays controlled will find nothing to cite or build on. I would not bring it to a reading group, would not cite it, and would not send it to peer review; it is a structural claim that belongs in the patent office, not a journal.

Referee Report

1 major / 0 minor

Summary. The manuscript claims a semiconductor die structure comprising a dielectric layer over integrated circuitry on a substrate, with a recessed moat in the dielectric upper surface filled with a first epoxy compound whose upper surface is coplanar with the dielectric and configured to exothermically react with a second epoxy, plus a conductive pad laterally surrounded by the moat whose top surface is recessed relative to the dielectric and electrically coupled to the circuitry at its bottom surface.

Significance. If the asserted geometry enables a controlled exothermic epoxy reaction that forms reliable bonds without exceeding the thermal budget of underlying circuitry, the approach could simplify die-to-die or die-to-substrate assembly by reducing the need for external heat sources. However, the manuscript supplies only a geometric and material-class description with no candidate compounds, enthalpies, peak-temperature estimates, or heat-flow analysis, so the functional performance remains unverified.

major comments (1)

Claim 1 (and the corresponding description): the central assertion that the first epoxy will undergo a controlled exothermic reaction sufficient to form a reliable bond without damaging circuitry or causing misalignment is unsupported; no specific epoxy identities, reaction stoichiometry, enthalpy values, or thermal-budget calculations are provided to substantiate that the peak temperature stays within acceptable limits for the semiconductor substrate.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the careful reading and constructive feedback. The manuscript is a patent disclosure centered on a novel die geometry that enables controlled exothermic epoxy bonding. We address the single major comment below.

read point-by-point responses

Referee: Claim 1 (and the corresponding description): the central assertion that the first epoxy will undergo a controlled exothermic reaction sufficient to form a reliable bond without damaging circuitry or causing misalignment is unsupported; no specific epoxy identities, reaction stoichiometry, enthalpy values, or thermal-budget calculations are provided to substantiate that the peak temperature stays within acceptable limits for the semiconductor substrate.

Authors: The disclosure is a structural patent application. Enablement is satisfied by describing the recessed moat geometry, coplanar epoxy fill, and recessed conductive pad that together confine the exothermic reaction volume and thermal path. Specific compound identities, stoichiometry, or numerical thermal budgets are not required for this claim scope; the invention resides in the arrangement that permits use of any suitable exothermic epoxy pair already known in the art while respecting semiconductor thermal limits. No experimental data section is expected or needed in a patent specification. revision: no

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: patent is a pure structural claim with no derivations or self-referential steps

full rationale

The document is a utility patent whose sole load-bearing content is a geometric/material specification (recessed moat, coplanar epoxy surface, recessed conductive pad). No equations, fitted parameters, predictions, ansatzes, or citations appear anywhere in the text. Consequently no step reduces to its own input by construction, and the circularity score is 0.

Assumptions & free parameters 0 free parameters · 1 assumptions · 0 invented entities

The patent rests on the domain assumption that exothermic epoxy reactions can be localized and controlled within a moat geometry without external process changes. No free parameters or invented physical entities are introduced.

assumptions (1)

domain assumption Exothermic reaction between the two specified epoxy compounds produces sufficient localized heat and bonding force to form a reliable mechanical and electrical joint.
Invoked in the abstract to justify the moat-and-pad geometry; no supporting thermal or mechanical data provided.

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Cite this review

Pith. "Pith review of Exothermic reactive bonding for semiconductor die assemblies and associated systems and methods." pith.science (2026). https://pith.science/paper/patent/us-12622335

@misc{pith2026patentus-12622335,
  author       = {Pith},
  title        = {Pith review of: Exothermic reactive bonding for semiconductor die assemblies and associated systems and methods},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/patent/us-12622335}},
  note         = {Machine review of arXiv:patent/us-12622335}
}

read the original abstract

1 . A semiconductor die, comprising: a semiconductor substrate including integrated circuitry; a dielectric layer over the semiconductor substrate, wherein at least a portion of an upper surface of the dielectric layer opposite the semiconductor substrate includes a recessed moat filled with a first epoxy compound configured to exothermically react with a second epoxy compound, the first epoxy compound having an upper surface coplanar with the upper surface of the dielectric layer; and a conductive pad in the dielectric layer laterally surrounded by moat filled with the first epoxy compound, the conductive pad including a top surface recessed with respect to the upper surface of the dielectric layer, wherein the conductive pad is coupled with the integrated circuitry at a bottom surface of the conductive pad opposite the top surface.

Figures

Figures reproduced from USPTO: patent/us-12622335 by the authors.

**Sheet 1.** Drawing sheet 1 from US 12622335. view at source ↗

**Sheet 2.** Drawing sheet 2 from US 12622335. view at source ↗

**Sheet 3.** Drawing sheet 3 from US 12622335. view at source ↗

Figures from the paper (1 more)

**Sheet 4.** Drawing sheet 4 from US 12622335.

Discussion (0). Continue with ORCID to comment.

Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

IndisputableMonolith.Cost.FunctionalEquation washburn_uniqueness_aczel unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

a recessed moat filled with a first epoxy compound configured to exothermically react with a second epoxy compound, the first epoxy compound having an upper surface coplanar with the upper surface of the dielectric layer; and a conductive pad in the dielectric layer laterally surrounded by moat filled with the first epoxy compound, the conductive pad including a top surface recessed with respect to the upper surface of the dielectric layer
IndisputableMonolith.Foundation.LedgerCanonicality ZeroParameterComparisonLedger unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

the conductive pad is coupled with the integrated circuitry at a bottom surface of the conductive pad opposite the top surface

What do these tags mean?

matches: The paper's claim is directly supported by a theorem in the formal canon.
supports: The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends: The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses: The paper appears to rely on the theorem as machinery.
contradicts: The paper's claim conflicts with a theorem or certificate in the canon.
unclear: Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

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Reviewed May 15, 2026 · model on record in the stance chip above.