Elaheh Sadredini

Identifiers

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Papers (3)

1. Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint cs.DC · 2017 · author #1
2. An Improved Scheme for Pre-computed Patterns in Core-based SoC Architecture cs.DC · 2017 · author #1
3. BILBO-friendly Hybrid BIST Architecture with Asymmetric Polynomial Reseeding cs.AR · 2017 · author #1

Mentions

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Frequent Coauthors

• Mahmood Fathy 3 shared papers
• Zainalabedin Navabi 2 shared papers
• Mohammad Hashem Haghbayan 1 shared papers
• Mohammadreza Najafi 1 shared papers
• Paniz Foroutan 1 shared papers
• Reza Rahimi 1 shared papers
• Zaialabedin Navabi 1 shared papers