Md Shabiul Islam

Identifiers

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Papers (2)

1. FPGA Implementation of pipeline Digit-Slicing Multiplier-Less Radix 2 power of 2 DIF SDF Butterfly for Fourier Transform Structure eess.SP · 2018 · author #4
2. VLSI Implementation of Novel Class of High Speed Pipelined Digital Signal Processing Filter for Wireless Receivers eess.SP · 2018 · author #4

Mentions

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Frequent Coauthors

• Masuri Othman 2 shared papers
• Rozita Teymourzadeh 2 shared papers
• Yazan Samir Algnabi 2 shared papers
• Mok Vee hong 1 shared papers