Paritosh K. Pandya
Identifiers
- name variant Paritosh K. Pandya 0.60 · backfill
Papers (8)
- Specification and Reactive Synthesis of Robust Controllers cs.LO · 2019 · author #1
- DCSYNTH: Guided Reactive Synthesis with Soft Requirements cs.LO · 2019 · author #2
- DCSYNTH: Guided Reactive Synthesis with Soft Requirements for Robust Controller and Shield Synthesis cs.LO · 2017 · author #2
- Formalizing Timing Diagram Requirements in Discrete Duration Calulus cs.LO · 2017 · author #2
- Deterministic Logics for UL cs.FL · 2014 · author #1
- On the Decidability and Complexity of Some Fragments of Metric Temporal Logic cs.LO · 2013 · author #3
- The Unary Fragments of Metric Interval Temporal Logic: Bounded versus Lower bound Constraints (Full Version) cs.LO · 2013 · author #1
- On Expressive Powers of Timed Logics: Comparing Boundedness, Non-punctuality and Deterministic Freezing cs.LO · 2011 · author #1
Mentions
Frequent Coauthors
- Amol Wakankar 4 shared papers
- Simoni S. Shah 3 shared papers
- Raj Mohan Matteplackel 2 shared papers
- Khushraj Madnani 1 shared papers
- Rajmohan Matteplackel 1 shared papers
- Shankara Narayanan Krishna 1 shared papers