Identifiers
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name variant
Saugata Ghose
0.60 · backfill
Papers (56)
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DARTH-PUM: A Hybrid Processing-Using-Memory Architecture
cs.AR · 2026 · author #3
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TCAM-SSD: A Framework for Search-Based Computing in Solid-State Drives
cs.AR · 2024 · author #6
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MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Processing
cs.AR · 2024 · author #6
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Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloud
cs.AR · 2022 · author #3
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Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases
cs.AR · 2022 · author #3
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Methodologies, Workloads, and Tools for Processing-in-Memory: Enabling the Adoption of Data-Centric Architectures
cs.AR · 2022 · author #3
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SeGraM: A Universal Hardware Accelerator for Genomic Sequence-to-Graph and Sequence-to-Sequence Mapping
cs.AR · 2022 · author #17
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Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Cooperation
cs.AR · 2022 · author #2
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Extending Memory Capacity in Consumer Devices with Emerging Non-Volatile Memory: An Experimental Study
cs.AR · 2021 · author #2
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Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks
cs.AR · 2021 · author #2
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CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations
cs.AR · 2021 · author #12
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SIMDRAM: An End-to-End Framework for Bit-Serial SIMD Computing in DRAM
cs.AR · 2021 · author #8
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DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
cs.AR · 2021 · author #4
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Polynesia: Enabling Effective Hybrid Transactional/Analytical Databases with Specialized Hardware/Software Co-Design
cs.AR · 2021 · author #2
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Mitigating Edge Machine Learning Inference Bottlenecks: An Empirical Study on Accelerating Google Edge Models
cs.AR · 2021 · author #2
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BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows
cs.CR · 2021 · author #11
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SIMDRAM: A Framework for Bit-Serial SIMD Processing Using DRAM
cs.AR · 2020 · author #8
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FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching
cs.AR · 2020 · author #5
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GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis
cs.AR · 2020 · author #15
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Accelerating Genome Analysis: A Primer on an Ongoing Journey
cs.AR · 2020 · author #5
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The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework
cs.AR · 2020 · author #5
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A Workload and Programming Ease Driven Perspective of Processing-in-Memory
cs.DC · 2019 · author #1
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Enabling Practical Processing in and near Memory for Data-Intensive Computing
cs.DC · 2019 · author #2
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Processing Data Where It Makes Sense: Enabling In-Memory Computation
cs.AR · 2019 · author #2
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Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study
cs.AR · 2019 · author #1
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Dataplant: Enhancing System Security with Low-Cost In-DRAM Value Generation Primitives
cs.CR · 2019 · author #14
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Enabling Efficient RDMA-based Synchronous Mirroring of Persistent Memory Transactions
cs.DC · 2018 · author #10
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Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation
cs.AR · 2018 · author #2
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What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study
cs.AR · 2018 · author #1
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Techniques for Efficiently Handling Power Surges in Fuel Cell Powered Data Centers: Modeling, Analysis, Results
cs.DC · 2018 · author #3
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Recent Advances in DRAM and Flash Memory Architectures
cs.AR · 2018 · author #2
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Recent Advances in Overcoming Bottlenecks in Memory Systems and Managing Memory Resources in GPU Systems
cs.AR · 2018 · author #2
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Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming
cs.AR · 2018 · author #2
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Read Disturb Errors in MLC NAND Flash Memory
cs.AR · 2018 · author #3
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SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure
cs.AR · 2018 · author #4
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LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency
cs.AR · 2018 · author #3
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Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency
cs.AR · 2018 · author #3
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Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips
cs.AR · 2018 · author #4
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Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory
cs.AR · 2018 · author #5
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Decoupling GPU Programming Models from Resource Management for Enhanced Programming Ease, Portability, and Performance
cs.DC · 2018 · author #6
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Mosaic: An Application-Transparent Hardware-Software Cooperative Memory Manager for GPUs
cs.OS · 2018 · author #4
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Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance
cs.AR · 2018 · author #2
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Zorua: Enhancing Programming Ease, Portability, and Performance in GPUs by Decoupling Programming Models from Resource Management
cs.DC · 2018 · author #6
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Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms, Future Research Directions
cs.AR · 2018 · author #1
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Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery
cs.AR · 2017 · author #2
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Nanopore Sequencing Technology and Tools for Genome Assembly: Computational Analysis of the Current State, Bottlenecks and Future Directions
q-bio.GN · 2017 · author #3
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GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies
q-bio.GN · 2017 · author #5
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Improving Multi-Application Concurrency Support Within the GPU Memory System
cs.AR · 2017 · author #5
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GRIM-filter: fast seed filtering in read mapping using emerging memory technologies
q-bio.GN · 2017 · author #5
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Using ECC DRAM to Adaptively Increase Memory Capacity
cs.AR · 2017 · author #2
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Error Characterization, Mitigation, and Recovery in Flash Memory Based Solid-State Drives
cs.AR · 2017 · author #2
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LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures
cs.AR · 2017 · author #2
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Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms
cs.AR · 2017 · author #3
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Understanding and Exploiting Design-Induced Latency Variation in Modern DRAM Chips
cs.AR · 2016 · author #4
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A Framework for Accelerating Bottlenecks in GPU Execution with Assist Warps
cs.AR · 2016 · author #4
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Simultaneous Multi Layer Access: A High Bandwidth and Low Cost 3D-Stacked Memory Interface
cs.AR · 2015 · author #4
Mentions
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2403.06938
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2012.11890
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