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Alfio Di Mauro

Identifiers

  • name variant Alfio Di Mauro 0.60 · backfill

Papers (15)

  1. Circuits and Systems for Embodied AI: Exploring uJ Multi-Modal Perception for Nano-UAVs on the Kraken Shield cs.AR · 2024 · author #2
  2. Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine cs.AR · 2023 · author #5
  3. ColibriUAV: An Ultra-Fast, Energy-Efficient Neuromorphic Edge Processing UAV-Platform with Event-Based and Frame-Based Cameras cs.CV · 2023 · author #4
  4. Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing cs.AR · 2023 · author #5
  5. ColibriES: A Milliwatts RISC-V Based Embedded System Leveraging Neuromorphic and Neural Networks Hardware Accelerators for Low-Latency Closed-loop Control Applications cs.AR · 2023 · author #3
  6. TCN-CUTIE: A 1036 TOp/s/W, 2.72 uJ/Inference, 12.2 mW All-Digital Ternary Accelerator in 22 nm FDX Technology cs.AR · 2022 · author #2
  7. An Energy-Efficient Spiking Neural Network for Finger Velocity Decoding for Implantable Brain-Machine Interface eess.SP · 2022 · author #4
  8. Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVs cs.AR · 2022 · author #1
  9. SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions cs.AR · 2022 · author #1
  10. Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode cs.AR · 2022 · author #5
  11. Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode cs.AR · 2021 · author #4
  12. An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes cs.AR · 2020 · author #4
  13. Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI cs.AR · 2020 · author #1
  14. Always-On 674uW @ 4GOP/s Error Resilient Binary Neural Networks with Aggressive SRAM Voltage Scaling on a 22nm IoT End-Node cs.AR · 2020 · author #1
  15. Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes cs.AR · 2020 · author #3

Mentions

  • 2410.09054 #2 · arxiv_oai · confidence 0.70 Alfio Di Mauro
  • 2312.14750 #5 · arxiv_oai · confidence 0.70 Alfio Di Mauro
  • 2305.08415 #5 · arxiv_oai · confidence 0.70 Alfio Di Mauro
  • 2305.18371 #4 · arxiv_oai · confidence 0.70 Alfio Di Mauro
  • 2201.08656 #5 · arxiv_oai · confidence 0.70 Alfio Di Mauro
  • 2302.07957 #3 · arxiv_oai · confidence 0.70 Alfio Di Mauro
  • 2212.00688 #2 · arxiv_oai · confidence 0.70 Alfio Di Mauro
  • 2210.06287 #4 · arxiv_oai · confidence 0.70 Alfio Di Mauro
  • 2209.01065 #1 · arxiv_oai · confidence 0.70 Alfio Di Mauro
  • 2204.10687 #1 · arxiv_oai · confidence 0.70 Alfio Di Mauro
  • 2110.09101 #4 · arxiv_oai · confidence 0.70 Alfio Di Mauro
  • 2010.04566 #4 · arxiv_oai · confidence 0.70 Alfio Di Mauro
  • 2007.13667 #1 · arxiv_oai · confidence 0.70 Alfio Di Mauro
  • 2007.08952 #1 · arxiv_oai · confidence 0.70 Alfio Di Mauro
  • 2006.14256 #3 · arxiv_oai · confidence 0.70 Alfio Di Mauro

Frequent Coauthors