STG generates deterministic testbenches 720x faster than iterative LLM flows with higher coverage and fewer false passes, while serving as an 11x faster data curation engine with 127x less energy.
AutoBench: Automatic testbench generation and evaluation using llms for hdl design
3 Pith papers cite this work. Polarity classification is still indexing.
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ChipSeek is a hierarchical-reward reinforcement learning framework with Curriculum-Guided Dynamic Policy Optimization that integrates EDA simulator feedback to improve LLM-generated RTL code on both functional correctness and PPA metrics.
LEGO extracts 42 standardized circuit skills from 11 open-source projects into a plug-and-play platform that raises Pass@1 from 0 to 0.805 on 41 hard VerilogEval v2 problems.
citing papers explorer
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Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation
STG generates deterministic testbenches 720x faster than iterative LLM flows with higher coverage and fewer false passes, while serving as an 11x faster data curation engine with 127x less energy.
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ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning
ChipSeek is a hierarchical-reward reinforcement learning framework with Curriculum-Guided Dynamic Policy Optimization that integrates EDA simulator feedback to improve LLM-generated RTL code on both functional correctness and PPA metrics.
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LEGO: An LLM Skill-Based Front-End Design Generation Platform
LEGO extracts 42 standardized circuit skills from 11 open-source projects into a plug-and-play platform that raises Pass@1 from 0 to 0.805 on 41 hard VerilogEval v2 problems.