HSCO-Bench is the first end-to-end benchmark for LLM agents performing hardware-software co-design of heterogeneous SoCs, where only two of five frontier models produced valid FPGA prototypes that underutilized available hardware resources.
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10 Pith papers cite this work, alongside 1,922 external citations. Polarity classification is still indexing.
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Pith papers citing it
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representative citing papers
Conditioning per-synapse weight dynamics on a memory-critical barrier via a Doob h-transform turns intrinsic analog device noise into a non-monotonic consolidation resource for continual learning.
Adaptive-frequency resonate-and-fire neurons perform sample-by-sample spectral estimation for FMCW radar, with memory scaling by number of targets rather than signal length.
Proposes RV32I-derived ISA and novel addressing for IMPLY memristive in-memory computing microcontrollers, with simulation energy evaluation and environmental sensor case study.
BMRUs enable analog recurrent neural network hardware via discrete outputs that suppress noise 20-fold, with one-to-one parameter-to-circuit mapping and linear power scaling for recurrence.
Replacing pointwise convolutions with DWHT yields a model with 79.1% fewer parameters, 48.4% fewer FLOPs, and 1.49% higher accuracy than MobileNet-V1 on CIFAR-100.
Soft matter systems are modeled as information channels of increasing complexity, yielding a heuristic thermodynamic ceiling on information processing performance and a performance gap to biology attributed to per-element energy scales.
KLR Hopfield networks exhibit robustness to quantization but sensitivity to pruning, interpreted as arising from dense bimodal parameterization of sparse input mappings.
citing papers explorer
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HSCO-Bench: An Agent-Driven End-to-End Hardware-Software Co-design Benchmark for Systems-on-Chip
HSCO-Bench is the first end-to-end benchmark for LLM agents performing hardware-software co-design of heterogeneous SoCs, where only two of five frontier models produced valid FPGA prototypes that underutilized available hardware resources.
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Intrinsic-Noise Consolidation: A Doob-Barrier-Conditioned Diffusion Turns Analog Device Noise into a Continual-Learning Resource
Conditioning per-synapse weight dynamics on a memory-critical barrier via a Doob h-transform turns intrinsic analog device noise into a non-monotonic consolidation resource for continual learning.
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Adaptive-Frequency Resonate-and-Fire Neurons for Spectral Estimation of Streaming Radar Signals
Adaptive-frequency resonate-and-fire neurons perform sample-by-sample spectral estimation for FMCW radar, with memory scaling by number of targets rather than signal length.
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An Instruction Set Architecture for IMPLY-based Memristive Processing-in-Array
Proposes RV32I-derived ISA and novel addressing for IMPLY memristive in-memory computing microcontrollers, with simulation energy evaluation and environmental sensor case study.
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Hardware-Software Co-Design of Scalable, Energy-Efficient Analog Recurrent Computations
BMRUs enable analog recurrent neural network hardware via discrete outputs that suppress noise 20-fold, with one-to-one parameter-to-circuit mapping and linear power scaling for recurrence.
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New pointwise convolution in Deep Neural Networks through Extremely Fast and Non Parametric Transforms
Replacing pointwise convolutions with DWHT yields a model with 79.1% fewer parameters, 48.4% fewer FLOPs, and 1.49% higher accuracy than MobileNet-V1 on CIFAR-100.
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Function, Complexity and Thermodynamics in Adaptive and Intelligent Soft Matter Systems: An Information-Theoretical Formulation
Soft matter systems are modeled as information channels of increasing complexity, yielding a heuristic thermodynamic ceiling on information processing performance and a performance gap to biology attributed to per-element energy scales.
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Quantization robustness from dense representations of sparse functions in high-capacity kernel associative memory
KLR Hopfield networks exhibit robustness to quantization but sensitivity to pruning, interpreted as arising from dense bimodal parameterization of sparse input mappings.
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