A recent proposal ACCORD [34] tries to make DRAM caches set-associative, to improve hit rate albeit at an expense of bandwidth and latency [35,36,37]

TOW ARDS SET-ASSOCIATIVE DESIGNS We evaluate our solutions in the context of a direct-mapped cache, but our designs, insights can be made applicable to set-associative caches

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To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches

cs.AR · 2019-07-04 · unverdicted · novelty 6.0

RRIP-AOB and ETR enable stateful replacement in 2GB DRAM caches for 18% speedup using <1KB SRAM by reducing state-tracking bandwidth 70%.

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To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches cs.AR · 2019-07-04 · unverdicted · none · ref 10
RRIP-AOB and ETR enable stateful replacement in 2GB DRAM caches for 18% speedup using <1KB SRAM by reducing state-tracking bandwidth 70%.

A recent proposal ACCORD [34] tries to make DRAM caches set-associative, to improve hit rate albeit at an expense of bandwidth and latency [35,36,37]

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