First hardware DTLS 1.3 implementation with reconfigurable prime-field ECC accelerator delivering 438x energy-efficiency gain over software and 44.08 uJ per handshake on a 65nm test chip.
Design and Implementation of Low-Area and Low-Power AES Encryptio n Hardware Core
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An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications
First hardware DTLS 1.3 implementation with reconfigurable prime-field ECC accelerator delivering 438x energy-efficiency gain over software and 44.08 uJ per handshake on a 65nm test chip.