AmpereOne implements MTE with zero tag-storage memory overhead and single-digit performance impact while identifying application memory management as the main remaining bottleneck.
Memory Tagging and how it improves C/C++ memory safety
2 Pith papers cite this work. Polarity classification is still indexing.
2
Pith papers citing it
abstract
Memory safety in C and C++ remains largely unresolved. A technique usually called "memory tagging" may dramatically improve the situation if implemented in hardware with reasonable overhead. This paper describes two existing implementations of memory tagging: one is the full hardware implementation in SPARC; the other is a partially hardware-assisted compiler-based tool for AArch64. We describe the basic idea, evaluate the two implementations, and explain how they improve memory safety. This paper is intended to initiate a wider discussion of memory tagging and to motivate the CPU and OS vendors to add support for it in the near future.
years
2025 2verdicts
UNVERDICTED 2representative citing papers
NanoTag enables byte-granular overflow detection on unmodified MTE binaries by combining hardware tagging with selective software tripwire checks on the Scudo allocator.
citing papers explorer
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Optimized Memory Tagging on AmpereOne Processors
AmpereOne implements MTE with zero tag-storage memory overhead and single-digit performance impact while identifying application memory management as the main remaining bottleneck.
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NanoTag: Systems Support for Efficient Byte-Granular Overflow Detection on ARM MTE
NanoTag enables byte-granular overflow detection on unmodified MTE binaries by combining hardware tagging with selective software tripwire checks on the Scudo allocator.