TRAM achieves up to 27% power reduction in multipliers for CNNs and vision transformers by jointly training model weights and approximate multiplier designs.
Simulation-guided ap- proximate logic synthesis under the maximum error constraint.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
citation-role summary
background 1
citation-polarity summary
fields
cs.LG 1years
2026 1verdicts
UNVERDICTED 1roles
background 1polarities
background 1representative citing papers
citing papers explorer
-
TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators
TRAM achieves up to 27% power reduction in multipliers for CNNs and vision transformers by jointly training model weights and approximate multiplier designs.