ADB-based AJSCC circuit with tunable spacing reduces power consumption and complexity versus prior parallel-VCVS design for 16+ levels according to LTSpice simulations.
A 190 nA bias current 10 mV input multistage boost regulator with intermediate-node control to supply RF blocks in self-powered wireless sensors
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Improved Circuit Design of Analog Joint Source Channel Coding for Low-power and Low-complexity Wireless Sensors
ADB-based AJSCC circuit with tunable spacing reduces power consumption and complexity versus prior parallel-VCVS design for 16+ levels according to LTSpice simulations.