Matching the size of pruned weight blocks to a systolic array lets edge transformer inference skip zero tiles, yielding up to 44% encoder speedup with roughly 1.4% WER degradation.
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Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems
Matching the size of pruned weight blocks to a systolic array lets edge transformer inference skip zero tiles, yielding up to 44% encoder speedup with roughly 1.4% WER degradation.