Pith. sign in

REVIEW 3 major objections 6 minor 38 references

Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems

T0 review · 3 major / 6 minor · reviewed 2026-08-12 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read Co-designing structured pruning with systolic array size speeds up edge transformer inference by up to 44% at a 1.4% word-error cost.

desk verdict A genuinely useful cross-stack study of pruning-tile size vs. systolic array size, but the headline QoS claim overreaches because the hardware multiplier's numerical error is never measured. read the letter →

arxiv 2411.10285 v2 pith:4CVWPWPK submitted 2024-11-15 cs.AR cs.AI

Pedro Palacios , Rafael Medina , Jean-Luc Rouas , Giovanni Ansaloni , David Atienza This is my paper · ORCID
classification cs.ARcs.AI
keywords systolicarraysstructuredpruninghardware-softwareco-designtransformersedgeAIquantizationspeechrecognitionmachinetranslation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper argues that structured pruning and systolic-array hardware should be co-designed so that the size of pruned weight blocks exactly matches the dimensions of the accelerator. When a weight tile is zeroed out, the entire tile's computation can be skipped, converting model sparsity directly into runtime and energy savings without needing extra sparsity-handling circuits. The authors build a three-tier co-design framework that prunes and quantizes transformer models, simulates the whole system, and synthesizes the accelerator hardware, then test it on speech recognition and machine translation transformers. On the LibriSpeech benchmark they report up to 44% speedup and 42% energy savings from a 20% pruning rate with 8-bit weights on a 32x32 array, at the cost of only 1.4% word error rate degradation. The key trade-off is that larger arrays give diminishing speedups for a fixed quality budget, because finding larger contiguous zero blocks becomes harder, while area and energy costs grow quadratically.

What carries the argument

The central mechanism is Systolic Array Structured Pruning (SASP), the practice of pruning whole tiles whose dimensions match the systolic array's, so that an all-zero weight tile can be skipped without specialized sparsity hardware. The supporting machinery is a three-tier co-design framework: an algorithmic tier that zeroes the lowest-L1-norm tiles and optionally quantizes weights to 8-bit integers; a system-simulation tier that measures runtime on a virtual platform with a tightly coupled systolic-array functional unit; and a hardware-synthesis tier that reports area, power, and energy from a synthesizable register-transfer-level template. The hardware tier also contributes a hybrid multiplier for 32-bit-float activations and 8-bit-integer weights that truncates the FP32 mantissa, multiplies it by the integer magnitude, and adjusts the exponent, while omitting subnormal numbers, infinities, and NaNs.

What would settle it

Run the synthesized accelerator, or a bit-accurate simulation of it, on the LibriSpeech test set through the full encoder and compare the resulting word error rate to the software-quantized value; a hardware-induced degradation far beyond 1.4 percentage points would refute the paper's headline quality-cost claim for the deployed system.

Watch

Extended reading notes

Core claim

Systolic Array Structured Pruning (SASP) is the claim that pruning transformer weights in blocks whose size equals the systolic array's dimensions lets an accelerator skip entire all-zero tiles, so sparsity translates into measured runtime and energy gains. On a weight-stationary systolic array, skipping a tile avoids both the cost of programming the weights and the cost of computing the associated partial results. Applied to an automatic speech recognition transformer on the LibriSpeech benchmark, a 20% structured pruning rate combined with 8-bit weight quantization yields a 44% system-wide speedup and 42% energy reduction at a word error rate near 5%, a 1.4-point rise from the 3.5% baseline; for a speech-to-text translation cascade on MuST-C, the comparable gains are 51% runtime and 34% energy savings with a 4-point BLEU loss. The paper also finds that speedups from enlarging the systolic array are sublinear at a fixed quality target, while area and energy grow quadratically, making SASP well suited for small, resource-constrained accelerators.

Load-bearing premise

The load-bearing premise is that the 1.4% word error rate degradation measured on the software-quantized model equals the true quality cost of the deployed system, even though the synthesized hardware multiplier approximates floating-point arithmetic and its added error was not measured.

Editorial extensions

If this is right

  • Edge devices can run transformer-based speech recognition and translation with materially lower latency and energy at a bounded accuracy cost, without adding sparse-matrix hardware.
  • For a fixed word-error-rate budget, smaller systolic arrays with moderate pruning can outperform larger arrays: scaling from 8x8 to 32x32 yields a 3x speedup but costs over 15x area and 4x energy, while SASP obtains comparable gains by skipping computation.
  • Pruning rates have an inflection point around 5% word error rate; beyond it, additional pruning causes steep quality loss for little speedup, so practical deployments should stay below that point.
  • Weight quantization to 8-bit integers compounds the benefits of pruning by letting four weights load per memory access, reducing area by about a third and further cutting energy.
  • The three-tier framework can be reused to explore other transformer workloads, other structured-sparsity granularities, and other pruning targets such as attention matrices.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The reported quality-of-service figures come from a software-quantized model, not from the actual synthesized accelerator; the hardware multiplier's truncated mantissa and its special-case zero handling could add error that the 1.4% degradation number does not include, so an end-to-end hardware measurement might show a larger quality cost.
  • The same block-matching idea could be applied to attention GEMMs or to patterns like 2:4 sparsity, provided the pattern aligns with the array dimensions; the paper restricts its pruning to feed-forward layers.
  • Because only the encoder is optimized, whole-model gains on the translation cascade may understate what full-stack SASP could achieve if the decoder were also pruned and accelerated.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. This paper proposes a cross-stack co-design framework called Systolic Array Structured Pruning (SASP), which matches the granularity of structured pruning tiles to the dimensions of a systolic array so that all-zero tiles can be skipped during GEMM computation. The framework combines algorithmic-level pruning and post-training INT8 weight quantization (via ESPnet/PyTorch), system-level performance simulation (via gem5-X with a custom systolic-array functional unit), and RTL synthesis of a systolic-array template with FP32 and hybrid FP32_INT8 multipliers. Using a LibriSpeech ASR transformer and a MuST-C speech-translation cascade, the authors report up to 44% speedup and 42% energy savings at a 5% WER QoS target, with an absolute WER degradation of about 1.4% relative to the unpruned, non-quantized model. The abstract and conclusion characterize these results as system-wide speedups.

Significance. If the reported numbers hold, SASP is a sensible and practically relevant design point: it avoids specialized sparse hardware and preserves regular memory layout while still exploiting structured sparsity. The systematic exploration across systolic-array sizes, pruning rates, and quantization schemes, together with the three-tier toolflow, is a useful contribution for edge-AI accelerator design. The paper is also commendable for reporting area/energy trade-offs and per-layer runtime behavior, and for making the QoS target explicit. However, the headline claims currently exceed the evidence: speedup measurements cover only the encoder, and QoS measurements are taken from a software-quantized model rather than from the approximate hardware multiplier. These gaps are fixable but require additional experiments or more carefully scoped claims.

major comments (3)
  1. [Abstract and Section 5] The 'system-wide speedup' claim is not supported by the measurements. Table 3 reports 'encoder speedup' and Fig. 10's caption specifies 'encoder inference speedup'; all speedup figures are for the encoder only, not for end-to-end inference including the decoder and non-accelerated components. Either provide end-to-end system measurements or change the wording in the abstract and conclusion to 'encoder speedup' or 'encoder-level speedup'.
  2. [Section 3.3 and Section 4.4] The QoS results are obtained from a software-quantized ESPnet model, not from the actual hybrid FP32_INT8 multiplier described in Section 3.3. That multiplier truncates the FP32 mantissa after alignment, does not handle subnormal numbers, and does not handle NaNs or infinities; no analysis is provided that quantifies the additional WER caused by these approximations. Since subnormal activations can occur in trained transformers, the reported 'only 1.4% WER degradation' may understate the deployed system's true quality loss. The paper should either emulate the multiplier's numerics in the QoS evaluation or provide error bounds, and temper the claim accordingly.
  3. [Section 3.3] The description of the hybrid multiplier is internally inconsistent: it first states that the design 'correctly computes the multiplication result, except for the case where either of the inputs equal to 0', then immediately states that 'infinities, NaNs, and subnormal numbers are not handled'. These two statements cannot both be true, because infinities, NaNs, and subnormals are valid IEEE-754 inputs that would not be correctly handled. Please clarify the exact behavior for special values and state precisely what 'correctly' means in this context.
minor comments (6)
  1. [Table 3 and Section 4.5] The 44% figure is obtained by comparing the FP32_INT8 SASP entry with the FP32_FP32 no-SASP entry of the same array size, while the table's stated baseline is 'a non-quantized baseline executed on CPU'. Please state the comparison baseline explicitly in the text and caption to avoid ambiguity.
  2. [Section 1, second paragraph] The phrase 'system-level level modeling' contains a duplicated word; it should read 'system-level modeling'.
  3. [Section 4.3, paragraph 2] The claim that inference runtime is 'strongly dominated by GEMM computations (exceeding 97% in all cases [2])' is cited from TiC-SAT [2] rather than measured for the specific ESPnet models used here; please verify this for the present workloads or add a qualifier.
  4. [Figure 7 caption] The caption should state that the improvements are relative to non-pruned quantized executions, as described in the text, rather than leaving the baseline implicit.
  5. [Section 3.3] The description of the hybrid multiplier does not mention the rounding mode used after the mantissa is truncated to 23 bits; since the numerical accuracy of the multiplier is central to the QoS claim, specifying the rounding behavior would be helpful.
  6. [Table 1] The QoS target of 5% WER is used to select pruning rates, but the paper does not report the variability of WER across test-set segments; providing error bars or confidence intervals would strengthen the comparison between operating points.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation found: the co-design study is empirical and self-contained, though the Section 3.3 multiplier approximation poses a correctness risk for the reported QoS, not a circularity.

full rationale

This paper is an empirical co-design study with no derivation chain that reduces to its inputs. The central claims are measurements: structured pruning and quantization are applied to ESPnet transformer models, WER/BLEU are then measured with ESPnet on the LibriSpeech/MuST-C test sets, and runtime/energy are measured with gem5 simulations and RTL synthesis of the authors' own systolic-array template. No equation or fitted parameter maps sparsity or quantization to QoS or speedup, so there is no 'prediction' that is forced by construction. The 20% pruning rate used in Table 3 is an operating point chosen at the 5% WER inflection point (Section 4.5), which is standard design-space exploration, not circular. The self-citations in Section 3.2, such as 'As in [2], we herein consider a weight-stationary scenario' and 'Similarly to [2], the functional unit employs dedicated instructions,' provide methodological precedent but are not load-bearing evidence for the reported speedup or QoS numbers, which come from the paper's own implementations against external benchmarks. I also flag, per the review rule, the limitation asserted in Section 3.3: the hybrid FP32_INT8 multiplier 'correctly computes the multiplication result, except for the case where either of the inputs equal to 0,' yet immediately adds that 'infinities, NaNs, and subnormal numbers are not handled.' Because the QoS results in Section 4.4 are obtained from software-quantized ESPnet models rather than from a cycle-accurate or bit-accurate model of this multiplier, the stated 1.4% WER degradation could understate the deployed system's quality loss. That is a correctness/evidence gap, not a circular reduction, so it does not increase the circularity score. Overall, no significant circularity is present.

Assumptions & free parameters 4 free parameters · 5 assumptions · 0 invented entities

The central results depend on a few domain assumptions about pruning sensitivity, simulation fidelity, and hardware multiplier accuracy. There are no fitted constants in a derivation sense; the reported operating point is chosen from a design-space sweep. The paper does not introduce new physical or conceptual entities.

free parameters (4)
  • QoS target for reported operating point = 5% WER
    The headline speedup is quoted at the 5% WER target from Table 1; choosing a looser or tighter QoS target changes the achievable speedup.
  • Structured pruning rate = 20%
    The 44% speedup point uses 20% of weight tiles zeroed; this rate is selected from a sweep to stay within the QoS target, not independently derived.
  • Systolic array size = 32x32
    The headline numbers correspond to the largest simulated array; speedup and energy vary substantially with array size.
  • Weight quantization scheme = FP32_INT8
    The headline combines 8-bit weight quantization with pruning; quantization alone contributes part of the speedup and energy savings.
assumptions (5)
  • domain assumption Zero weight tiles are exactly zero after pruning, so skipping them in the systolic array is numerically lossless.
    Section 3.1 prunes entire tiles to zero and Section 3.2 skips all-zero tiles; this is true by construction, but assumes the pruning mask is applied before inference.
  • domain assumption Tiles with the lowest L1-norm are the least important for quality of service.
    Section 3.1 prunes the lowest-L1-norm tiles globally; the paper validates this empirically via WER curves, but it is a modeling choice, not a theorem.
  • domain assumption gem5 simulation with the custom functional unit and 1 GHz single-core configuration faithfully models runtime of the accelerated system.
    Section 3.2 and Table 2 define the simulated system; no validation against real hardware or RTL co-simulation is presented.
  • domain assumption The approximate FP32_INT8 hardware multiplier does not materially change the measured QoS.
    Section 3.3 describes mantissa truncation and lack of subnormal, NaN, and infinity handling; Section 4.4 reports WER from software quantization, not from the hardware multiplier.
  • domain assumption GEMM execution dominates inference time (over 97%), so encoder speedups can be treated as representative of system-level gains.
    Section 4.3 cites reference [2] for the 97% figure; the abstract's 'system-wide' claim relies on this extrapolation.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems." pith.science (2026). https://pith.science/paper/4CVWPWPK

@misc{pith2026241110285,
  author       = {Pith},
  title        = {Pith review of: Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/4CVWPWPK}},
  note         = {Machine review of arXiv:2411.10285}
}
read the original abstract

Efficient deployment of resource-intensive transformers on edge devices necessitates cross-stack optimization. We thus study the interrelation between structured pruning and systolic acceleration, matching the size of pruned blocks with the systolic array dimensions. In this setting, computations of pruned weight blocks can be skipped, reducing run-time and energy consumption, but potentially impacting quality of service (QoS). To evaluate the trade-offs between systolic array size and sparsity opportunities, we present a novel co-design framework that integrates algorithmic optimization, system simulation, and hardware design. Targeting speech recognition and machine translation using transformers as case study, we analyze how configuration choices across the stack affect performance metrics. Results demonstrate that structured pruning on systems featuring systolic array acceleration can effectively increase performance, while maintaining high QoS levels. Up to 44% system-wide speedups due to structured pruning and quantization were measured, with only 1.4% word error rate degradation on the standard LibriSpeech dataset.

Figures

Figures reproduced from arXiv: 2411.10285 by the authors.

Figure 1
Figure 1. Qualitative radar plot illustrating two SASP solu [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 4
Figure 4. Architectural diagram of the systolic array, sup [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 2
Figure 2. Overview of Hardware-Software co-design frame [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figures from the paper (7 more)
Figure 3
Figure 3. Figure 3: Tiled matrix multiplication with structured prun [PITH_FULL_IMAGE:figures/full_fig_p003_3.png]
Figure 5
Figure 5. Figure 5: Hardware diagram of the hybrid FP32_INT8 multi￾plier. This logic is bypassed in case any of the operands is equal to zero. 3.3 Systolic Array Architecture The systolic array hardware implementation, depicted in Figure ( [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]
Figure 7
Figure 7. Figure 7: Speedup and energy improvements from Systolic [PITH_FULL_IMAGE:figures/full_fig_p005_7.png]
Figure 6
Figure 6. Figure 6: Synthesis results for the systolic array design across [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]
Figure 9
Figure 9. Figure 9: Achieved Word Error Rate when varying the per [PITH_FULL_IMAGE:figures/full_fig_p006_9.png]
Figure 10
Figure 10. Figure 10: Trade-offs among encoder inference speedup, area [PITH_FULL_IMAGE:figures/full_fig_p006_10.png]
Figure 11
Figure 11. Figure 11: Speedup with respect to software execution of the [PITH_FULL_IMAGE:figures/full_fig_p007_11.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

38 extracted references · 23 canonical work pages

  1. [1]

    Alireza Amirshahi, Giovanni Ansaloni, and David Atienza. 2024. Accelerator- Driven Data Arrangement to Minimize Transformers Run-Time on Multi-Core Architectures. In 15th Workshop on Parallel Programming and Run-Time Manage- ment Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Pla...

    work page 2024

  2. [2]

    Alireza Amirshahi, Joshua Alexander Harrison Klein, Giovanni Ansaloni, and David Atienza. 2023. TiC-SAT: Tightly-coupled Systolic Accelerator for Trans- formers. In 2023 28th Asia and South Pacific Design Automation Conference (ASP- DAC). 657–663

    work page 2023

  3. [3]

    Bahar Asgari, Ramyad Hadidi, Hyesoon Kim, and Sudhakar Yalamanchili. 2019. ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays. IEEE Micro 39, 5 (2019), 46–54. doi:10.1109/MM.2019.2930057

    arXiv 2019

  4. [4]

    Leila Ben Letaifa and Jean-Luc Rouas. 2023. Variable Scale Pruning for Trans- former Model Compression in End-to-End Speech Recognition. Algorithms 16, 9 (2023), 398

    work page 2023

  5. [5]

    Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R

    Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, and David A. Wood. 2011. The gem5 simulator. SIGARCH Comput. Archit. News 39, 2 (Aug. 2011), 1–7. doi:10.1145/2024716.2024718

    arXiv 2011

  6. [6]

    Klaiber, Daniel Mueller-Gritschneder, Paul Palomero Bernardo, Sebastian Prebeck, and Muham- mad Shafique

    Oliver Bringmann, Wolfgang Ecker, Ingo Feldner, Adrian Frischknecht, Christoph Gerum, Timo Hämäläinen, Muhammad Abdullah Hanif, Michael J. Klaiber, Daniel Mueller-Gritschneder, Paul Palomero Bernardo, Sebastian Prebeck, and Muham- mad Shafique. 2021. Automated HW/SW Co-design for Edge AI: State, Challenges and Steps Ahead: Special Session Paper. In2021 In...

    work page 2021

  7. [7]

    Tom B. Brown, Benjamin Mann, Nick Ryder, Melanie Subbiah, Jared Kaplan, Prafulla Dhariwal, Arvind Neelakantan, Pranav Shyam, Girish Sastry, Amanda Askell, Sandhini Agarwal, Ariel Herbert-Voss, Gretchen Krueger, Tom Henighan, Rewon Child, Aditya Ramesh, Daniel M. Ziegler, Jeffrey Wu, Clemens Winter, Christopher Hesse, Mark Chen, Eric Sigler, Mateusz Litwin...

    2020

  8. [8]

    Krishna Teja Chitty-Venkata, Sparsh Mittal, Murali Emani, Venkatram Vish- wanath, and Arun K Somani. 2023. A survey of techniques for optimizing transformer inference. Journal of Systems Architecture (2023), 102990

    work page 2023

Show all 38 references
  1. [9]

    Di Gangi, Roldano Cattoni, Luisa Bentivogli, Matteo Negri, and Marco Turchi

    Mattia A. Di Gangi, Roldano Cattoni, Luisa Bentivogli, Matteo Negri, and Marco Turchi. 2019. MuST-C: a Multilingual Speech Translation Corpus. In Proceedings of the 2019 Conference of the North American Chapter of the Association for Com- putational Linguistics: Human Language...

    2019 doi

  2. [10]

    Alexey Dosovitskiy, Lucas Beyer, Alexander Kolesnikov, Dirk Weissenborn, Xi- aohua Zhai, Thomas Unterthiner, Mostafa Dehghani, Matthias Minderer, Georg Heigold, Sylvain Gelly, et al . 2020. An Image is Worth 16x16 Words: Trans- formers for Image Recognition at Scale. In Intern...

    2020

  3. [11]

    Juan Gómez-Luna, Izzat El Hajj, Ivan Fernandez, Christina Giannoula, Geraldo F Oliveira, and Onur Mutlu. 2021. Benchmarking memory-centric computing sys- tems: Analysis of real processing-in-memory hardware. In2021 12th International Green and Sustainable Computing Conference ...

    2021

  4. [12]

    Pengcheng Guo, Florian Boyer, Xuankai Chang, Tomoki Hayashi, Yosuke Higuchi, Hirofumi Inaguma, Naoyuki Kamo, Chenda Li, Daniel Garcia-Romero, Jiatong Shi, Jing Shi, Shinji Watanabe, Kun Wei, Wangyou Zhang, and Yuekai Zhang

  5. [13]

    Nitthilan Kannappan Jayakodi, Janardhan Rao Doppa, and Partha Pratim Pande

  6. [14]

    Hyeong-Ju Kang. 2019. Accelerator-aware pruning for convolutional neural networks. IEEE Transactions on Circuits and Systems for Video Technology 30, 7 (2019), 2093–2103

    2019

  7. [15]

    In 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)

    A General Hardware and Software Co-Design Framework for Energy- Efficient Edge AI. In 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). 1–7. doi:10.1109/ICCAD51958.2021.9643557

    2021

  8. [16]

    Bingbing Li, Zhenglun Kong, Tianyun Zhang, Ji Li, Zhengang Li, Hang Liu, and Caiwen Ding. 2020. Efficient transformer-based large scale language rep- resentations using hardware-friendly block structured pruning. arXiv preprint arXiv:2009.08065 (2020)

    2020 arXiv

  9. [17]

    Joshua Klein, Irem Boybat, Yasir Mahmood Qureshi, Martino Dazzi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Abu Sebastian, and David Atienza

  10. [18]

    Zhi-Gang Liu, Paul N Whatmough, and Matthew Mattina. 2020. Systolic ten- sor array: An efficient structured-sparse GEMM accelerator for mobile CNN inference. IEEE Computer Architecture Letters 19, 1 (2020), 34–37

    2020

  11. [19]

    Liqiang Lu, Yicheng Jin, Hangrui Bi, Zizhang Luo, Peng Li, Tao Wang, and Yun Liang. 2021. Sanger: A co-design framework for enabling sparse attention using reconfigurable architecture. In MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture. 977–991

    2021

  12. [20]

    Tailin Liang, John Glossner, Lei Wang, Shaobo Shi, and Xiaotong Zhang. 2021. Pruning and quantization for deep neural network acceleration: A survey. Neu- rocomputing 461 (2021), 370–403

    2021

  13. [21]

    Rafael Medina Morillas, Saeideh Alinezhad Chamazcoti, Marina Zapater San- cho, Giovanni Ansaloni, Timon Evenblij, Alexandre Sébastien Julien Levisse, Dwaipayan Biswas, Francky Catthoor, and David Atienza Alonso. 2024. Bank on Compute-near-Memory: Design Space Exploration of Pr...

    2024

  14. [22]

    Vassil Panayotov, Guoguo Chen, Daniel Povey, and Sanjeev Khudanpur. 2015. Librispeech: An ASR corpus based on public domain audio books. In 2015 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) . 5206–5210. doi:10.1109/ICASSP.2015.7178964

    2015

  15. [23]

    Xiaolong Ma, Sheng Lin, Shaokai Ye, Zhezhi He, Linfeng Zhang, Geng Yuan, Sia Huat Tan, Zhengang Li, Deliang Fan, Xuehai Qian, et al. 2021. Non-structured DNN weight pruning—Is it beneficial in any platform?IEEE transactions on neural networks and learning systems 33, 9 (2021),...

    2021

  16. [24]

    Yasir Mahmood Qureshi, William Andrew Simon, Marina Zapater, David Atienza, and Katzalin Olcoz. 2019. Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms. In 2019 Spring Simulation Confer- ence (SpringSim). 1–12. doi:10.23919/SpringSim.2019.8732862

    2019

  17. [25]

    Katie Spoon, Hsinyu Tsai, An Chen, Malte J Rasch, Stefano Ambrogio, Charles Mackin, Andrea Fasoli, Alexander M Friz, Pritish Narayanan, Milos Stanisavl- jevic, et al. 2021. Toward software-equivalent accuracy on transformer-based deep neural networks with analog memory devices...

    2021

  18. [26]

    Adam Paszke, Sam Gross, Francisco Massa, Adam Lerer, James Bradbury, Gregory Chanan, Trevor Killeen, Zeming Lin, Natalia Gimelshein, Luca Antiga, Alban Desmaison, Andreas Köpf, Edward Yang, Zach DeVito, Martin Raison, Alykhan Tejani, Sasank Chilamkurthy, Benoit Steiner, Lu Fan...

    2019

  19. [27]

    Minjin Tang, Mei Wen, Jianchao Yang, Zeyu Xue, and Junzhong Shen. 2024. SPSA: Exploring Sparse-Packing Computation on Systolic Arrays From Scratch. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2024)

    2024

  20. [28]

    Shikhar Tuli, Chia-Hao Li, Ritvik Sharma, and Niraj K. Jha. 2023. CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework. ACM Trans. Embed. Comput. Syst. 22, 3, Article 51 (April 2023), 30 pages. doi:10.1145/ 3575798

    2023

  21. [29]

    Wenhao Sun, Deng Liu, Zhiwei Zou, Wendi Sun, Song Chen, and Yi Kang. 2023. Sense: Model-hardware codesign for accelerating sparse CNNs on systolic arrays. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31, 4 (2023), 470–483

    2023

  22. [30]

    Tom Verbeure. [n. d.]. Fpxx Library. https://github.com/tomverbeure/math

  23. [31]

    Shinji Watanabe, Takaaki Hori, Shigeki Karita, Tomoki Hayashi, Jiro Nishitoba, Yuya Unno, Nelson Enrique Yalta Soplin, Jahn Heymann, Matthew Wiesner, Nanxin Chen, Adithya Renduchintala, and Tsubasa Ochiai. 2018. ESPnet: End-to- End Speech Processing Toolkit. In Proceedings of ...

    2018

  24. [32]

    Gomez, Łukasz Kaiser, and Illia Polosukhin

    Ashish Vaswani, Noam Shazeer, Niki Parmar, Jakob Uszkoreit, Llion Jones, Aidan N. Gomez, Łukasz Kaiser, and Illia Polosukhin. 2017. Attention is all you need. In Proceedings of the 31st International Conference on Neural Information Processing Systems (Long Beach, California, ...

    2017

  25. [33]

    Sam (Likun) Xi, Yuan Yao, Kshitij Bhardwaj, Paul Whatmough, Gu-Yeon Wei, and David Brooks. 2020. SMAUG: End-to-End Full-Stack Simulation Infrastructure for Deep Learning Workloads. ACM Trans. Archit. Code Optim. 17, 4, Article 39 (Nov. 2020), 26 pages. doi:10.1145/3424669

    2020 doi

  26. [34]

    Rui Xu, Sheng Ma, Yang Guo, and Dongsheng Li. 2023. A Survey of Design and Optimization for Systolic Array-based DNN Accelerators. ACM Comput. Surv. 56, 1, Article 20 (Aug. 2023), 37 pages. doi:10.1145/3604802

    2023 doi

  27. [35]

    Wei Wen, Chunpeng Wu, Yandan Wang, Yiran Chen, and Hai Li. 2016. Learning structured sparsity in deep neural networks. In Proceedings of the 30th Interna- tional Conference on Neural Information Processing Systems (Barcelona, Spain) (NIPS’16). Curran Associates Inc., Red Hook,...

    2016

  28. [38]

    Jiecao Yu, Andrew Lukefahr, David Palframan, Ganesh Dasika, Reetuparna Das, and Scott Mahlke. 2017. Scalpel: Customizing DNN pruning to the underlying hardware parallelism. In 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA). 548–560. doi:10.11...

    2017

  29. [2021]

    In IEEE International Conference on Acoustics, Speech and Signal Processing

    Recent Developments on Espnet Toolkit Boosted By Conformer. In IEEE International Conference on Acoustics, Speech and Signal Processing . 5874–5878. doi:10.1109/ICASSP39728.2021.9414858

    2021

  30. [2022]

    IEEE Trans

    Alpine: Analog in-memory acceleration with tight processor integration for deep learning. IEEE Trans. Comput. 72, 7 (2022), 1985–1998

    2022

Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.