Scratchpad memory cuts memory traffic 8x in CGRAs; homogeneous designs show 4.4-8.2x lower area overhead and up to 5x higher speed than heterogeneous ones for matrix kernels while running at 700 MHz.
VWR2A: a very-wide-register reconfigurable-array architecture for low-power embedded devices,
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
cs.AR 1years
2026 1verdicts
UNVERDICTED 1representative citing papers
citing papers explorer
-
Evaluating Architectural Trade-offs in CGRAs: The Impact of Scratchpad Memory and Heterogeneity on Compute-Intensive Kernels
Scratchpad memory cuts memory traffic 8x in CGRAs; homogeneous designs show 4.4-8.2x lower area overhead and up to 5x higher speed than heterogeneous ones for matrix kernels while running at 700 MHz.