CMOS field-programmable spiking neural network with LIF neurons, integrated VCOs, and on-chip FPGA implements hardware reservoir computing, demonstrated via FORCE learning and NARMA10 tasks with 21.7 pJ/pulse energy and 540 NAND2 area per neuron.
Express252401–2412 URL https://opg.optica.org/oe/abstract.cfm?URI=oe-25-3-2401
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CMOS Implementation of Field Programmable Spiking Neural Network for Hardware Reservoir Computing
CMOS field-programmable spiking neural network with LIF neurons, integrated VCOs, and on-chip FPGA implements hardware reservoir computing, demonstrated via FORCE learning and NARMA10 tasks with 21.7 pJ/pulse energy and 540 NAND2 area per neuron.