TimingLLM uses a fine-tuned LLM to generate structural timing cues from Verilog followed by a retrieval-augmented regressor with a learned steering vector to predict WNS and TNS with R values of 0.91 and 0.97.
Craftrtl: High-quality synthetic data generation for verilog code models with correct-by- construction non-textual representations and targeted code repair
2 Pith papers cite this work. Polarity classification is still indexing.
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ChipSeek is a hierarchical-reward reinforcement learning framework with Curriculum-Guided Dynamic Policy Optimization that integrates EDA simulator feedback to improve LLM-generated RTL code on both functional correctness and PPA metrics.
citing papers explorer
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TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog
TimingLLM uses a fine-tuned LLM to generate structural timing cues from Verilog followed by a retrieval-augmented regressor with a learned steering vector to predict WNS and TNS with R values of 0.91 and 0.97.
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ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning
ChipSeek is a hierarchical-reward reinforcement learning framework with Curriculum-Guided Dynamic Policy Optimization that integrates EDA simulator feedback to improve LLM-generated RTL code on both functional correctness and PPA metrics.