ESBMC-GraphPLC implements a graph traversal resolver that extracts Boolean rung logic from graphical LD connection graphs and produces complete GOTO IR, enabling verification of programs that previously yielded empty representations.
Automated verification of temporal properties of ladder programs
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ESBMC-GraphPLC: Formal Verification of Graphical PLCopen XML Ladder Diagram Programs Using SMT-Based Model Checking
ESBMC-GraphPLC implements a graph traversal resolver that extracts Boolean rung logic from graphical LD connection graphs and produces complete GOTO IR, enabling verification of programs that previously yielded empty representations.