ESBMC-PLC+ unifies support for all major IEC 61131-3 formats (ST, LD, SCL) in a single ESBMC backend with k-induction for unbounded safety proofs and extended function block semantics.
Formal analysis of networked PLC controllers interacting with physical environments
2 Pith papers cite this work. Polarity classification is still indexing.
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Pith papers citing it
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cs.PL 2years
2026 2representative citing papers
ESBMC-GraphPLC implements a graph traversal resolver that extracts Boolean rung logic from graphical LD connection graphs and produces complete GOTO IR, enabling verification of programs that previously yielded empty representations.
citing papers explorer
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ESBMC-PLC+: A Unified IEC 61131-3 Formal Verification Framework as a PLCverif Successor
ESBMC-PLC+ unifies support for all major IEC 61131-3 formats (ST, LD, SCL) in a single ESBMC backend with k-induction for unbounded safety proofs and extended function block semantics.
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ESBMC-GraphPLC: Formal Verification of Graphical PLCopen XML Ladder Diagram Programs Using SMT-Based Model Checking
ESBMC-GraphPLC implements a graph traversal resolver that extracts Boolean rung logic from graphical LD connection graphs and produces complete GOTO IR, enabling verification of programs that previously yielded empty representations.