First hardware DTLS 1.3 implementation with reconfigurable prime-field ECC accelerator delivering 438x energy-efficiency gain over software and 44.08 uJ per handshake on a 65nm test chip.
340 mV1.1 V , 289 Gbps/W, 2090-Gate Nan oAES Hardware Accelerator With Area-Optimized Encrypt/Decryp t GF (24)2 Polynomials in 22 nm Tri-Gate CMOS
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An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications
First hardware DTLS 1.3 implementation with reconfigurable prime-field ECC accelerator delivering 438x energy-efficiency gain over software and 44.08 uJ per handshake on a 65nm test chip.