A RISC-V-controlled self-calibration technique in a mixed-signal CIM accelerator SoC fabricated in 22-nm FDSOI improves compute SNR by 25-45% to reach 18-24 dB.
His research is in analog circuit design for AI accelerators with focus on Sample and Hold circuits, analog memories, and noise analysis
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Acore-CIM: build accurate and reliable mixed-signal CIM cores with RISC-V controlled self-calibration
A RISC-V-controlled self-calibration technique in a mixed-signal CIM accelerator SoC fabricated in 22-nm FDSOI improves compute SNR by 25-45% to reach 18-24 dB.