A RISC-V-controlled self-calibration technique in a mixed-signal CIM accelerator SoC fabricated in 22-nm FDSOI improves compute SNR by 25-45% to reach 18-24 dB.
A 40-nm Compute-in-Memory Macro With RRAM Addressing IR Drop and Off- State Current
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
cs.AR 1years
2025 1verdicts
UNVERDICTED 1representative citing papers
citing papers explorer
-
Acore-CIM: build accurate and reliable mixed-signal CIM cores with RISC-V controlled self-calibration
A RISC-V-controlled self-calibration technique in a mixed-signal CIM accelerator SoC fabricated in 22-nm FDSOI improves compute SNR by 25-45% to reach 18-24 dB.