pith. sign in

arxiv: 1410.2237 · v2 · pith:2RG5E6VOnew · submitted 2014-10-08 · ❄️ cond-mat.mes-hall

Nanoscale Electrostatic Control of Oxide Interfaces

classification ❄️ cond-mat.mes-hall
keywords gateconductingdemonstratedeviceelectrostaticgatesinterfacesnanoscale
0
0 comments X
read the original abstract

We develop a robust and versatile platform to define nanostructures at oxide interfaces via patterned top gates. Using LaAlO$_3$/SrTiO$_3$ as a model system, we demonstrate controllable electrostatic confinement of electrons to nanoscale regions in the conducting interface. The excellent gate response, ultra-low leakage currents, and long term stability of these gates allow us to perform a variety of studies in different device geometries from room temperature down to 50 mK. Using a split-gate device we demonstrate the formation of a narrow conducting channel whose width can be controllably reduced via the application of appropriate gate voltages. We also show that a single narrow gate can be used to induce locally a superconducting to insulating transition. Furthermore, in the superconducting regime we see indications of a gate-voltage controlled Josephson effect.

This paper has not been read by Pith yet.

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.